[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Luke Lau via llvm-commits]

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@@ -1502,14 +1668,14 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
   // we need to prove the value is available at the point we're going
   // to insert the vsetvli at.
   if (AvailableInfo.hasAVLReg()) {
-    const MachineInstr *AVLDefMI = &AvailableInfo.getAVLDefMI();
+    SlotIndex SI = AvailableInfo.getAVLVNInfo()->def;
     // This is an inline dominance check which covers the case of
     // UnavailablePred being the preheader of a loop.
-    if (AVLDefMI->getParent() != UnavailablePred)
+    if (LIS->getMBBFromIndex(SI) != UnavailablePred)
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lukel97 wrote:

We won't have LiveIntervals here if `-riscv-vsetvli-after-rvv-regalloc` is set to false, we would need to keep around the old pre-ra path and use getUniqueVRegDef

But what do you think about just removing the flag and pre-ra code paths entirely? It would allow us to simplify things here a good bit, and if we need to reverting should be straightforward since the code changes are only in RISCVInsertVSETVLI.cpp.

I can bring this up for discussion in the next RISC-V sync up call

https://github.com/llvm/llvm-project/pull/70549