[llvm] [LangRef] Clarify semantics of masked vector load/store (PR #82469)

[Ralf Jung via llvm-commits]

https://github.com/RalfJung updated https://github.com/llvm/llvm-project/pull/82469

>From 9c21fa788618d1acbe930f56c15a4759aa7e537f Mon Sep 17 00:00:00 2001
From: Ralf Jung <post at ralfj.de>
Date: Thu, 2 May 2024 09:07:32 +0200
Subject: [PATCH 1/2] clarify semantics of masked vector load/store

---
 llvm/docs/LangRef.rst | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 6291a4e57919a5..fd25e3a11da9df 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -24419,7 +24419,10 @@ Semantics:
 """"""""""
 
 The '``llvm.masked.load``' intrinsic is designed for conditional reading of selected vector elements in a single IR operation. It is useful for targets that support vector masked loads and allows vectorizing predicated basic blocks on these targets. Other targets may support this intrinsic differently, for example by lowering it into a sequence of branches that guard scalar load operations.
-The result of this operation is equivalent to a regular vector load instruction followed by a 'select' between the loaded and the passthru values, predicated on the same mask. However, using this intrinsic prevents exceptions on memory access to masked-off lanes.
+The result of this operation is equivalent to a regular vector load instruction followed by a 'select' between the loaded and the passthru values, predicated on the same mask, except that the masked-off lanes are not accessed.
+Only the masked-on lanes of the vector need to be inbounds of an allocation (but all these lanes need to be inbounds of the same allocation).
+In particular, using this intrinsic prevents exceptions on memory accesses to masked-off lanes.
+Masked-off lanes are also not considered accessed for the purpose of data races or `noalias` constraints.
 
 
 ::
@@ -24461,7 +24464,10 @@ Semantics:
 """"""""""
 
 The '``llvm.masked.store``' intrinsics is designed for conditional writing of selected vector elements in a single IR operation. It is useful for targets that support vector masked store and allows vectorizing predicated basic blocks on these targets. Other targets may support this intrinsic differently, for example by lowering it into a sequence of branches that guard scalar store operations.
-The result of this operation is equivalent to a load-modify-store sequence. However, using this intrinsic prevents exceptions and data races on memory access to masked-off lanes.
+The result of this operation is equivalent to a load-modify-store sequence, except that the masked-off lanes are not accessed.
+Only the masked-on lanes of the vector need to be inbounds of an allocation (but all these lanes need to be inbounds of the same allocation).
+In particular, using this intrinsic prevents exceptions on memory accesses to masked-off lanes.
+Masked-off lanes are also not considered accessed for the purpose of data races or `noalias` constraints.
 
 ::
 

>From b772a03b1b9141d1352ecfd4aeb98d42f3ddaa96 Mon Sep 17 00:00:00 2001
From: Ralf Jung <post at ralfj.de>
Date: Fri, 3 May 2024 07:42:32 +0200
Subject: [PATCH 2/2] formatting

Co-authored-by: Nikita Popov <github at npopov.com>
---
 llvm/docs/LangRef.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index fd25e3a11da9df..05c0c77866cbc0 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -24422,7 +24422,7 @@ The '``llvm.masked.load``' intrinsic is designed for conditional reading of sele
 The result of this operation is equivalent to a regular vector load instruction followed by a 'select' between the loaded and the passthru values, predicated on the same mask, except that the masked-off lanes are not accessed.
 Only the masked-on lanes of the vector need to be inbounds of an allocation (but all these lanes need to be inbounds of the same allocation).
 In particular, using this intrinsic prevents exceptions on memory accesses to masked-off lanes.
-Masked-off lanes are also not considered accessed for the purpose of data races or `noalias` constraints.
+Masked-off lanes are also not considered accessed for the purpose of data races or ``noalias`` constraints.
 
 
 ::
@@ -24467,7 +24467,7 @@ The '``llvm.masked.store``' intrinsics is designed for conditional writing of se
 The result of this operation is equivalent to a load-modify-store sequence, except that the masked-off lanes are not accessed.
 Only the masked-on lanes of the vector need to be inbounds of an allocation (but all these lanes need to be inbounds of the same allocation).
 In particular, using this intrinsic prevents exceptions on memory accesses to masked-off lanes.
-Masked-off lanes are also not considered accessed for the purpose of data races or `noalias` constraints.
+Masked-off lanes are also not considered accessed for the purpose of data races or ``noalias`` constraints.
 
 ::