[clang] [llvm] [AMDGPU][WIP] Add support for i64/f64 readlane, writelane and readfirstlane operations. (PR #89217)

[Matt Arsenault via llvm-commits]

================
@@ -5386,6 +5386,94 @@ bool AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
   return true;
 }
 
+bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
+                                         MachineInstr &MI,
+                                         Intrinsic::ID IID) const {
+
+  MachineIRBuilder &B = Helper.MIRBuilder;
+  MachineRegisterInfo &MRI = *B.getMRI();
+
+  Register DstReg = MI.getOperand(0).getReg();
+  Register Src0 = MI.getOperand(2).getReg();
+
+  LLT Ty = MRI.getType(DstReg);
+  unsigned Size = Ty.getSizeInBits();
+
+  if (Size == 32)
+    return true;
+
+  if (Size < 32) {
+    auto Ext = B.buildAnyExt(LLT::scalar(32), Src0).getReg(0);
+    auto LaneOpDst =
+        B.buildIntrinsic(Intrinsic::amdgcn_readlane, {S32}).addUse(Ext);
+    if (IID == Intrinsic::amdgcn_readlane ||
+        IID == Intrinsic::amdgcn_writelane) {
+      auto Src1 = MI.getOperand(3).getReg();
+      LaneOpDst = LaneOpDst.addUse(Src1);
+      if (IID == Intrinsic::amdgcn_writelane) {
+        auto Src2 = MI.getOperand(4).getReg();
+        auto Ext2 = B.buildAnyExt(LLT::scalar(32), Src2).getReg(0);
+        LaneOpDst = LaneOpDst.addUse(Ext2);
+      }
+    }
+    B.buildTrunc(DstReg, LaneOpDst).getReg(0);
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arsenm wrote:

The .getReg(0) does nothing here 

https://github.com/llvm/llvm-project/pull/89217