[clang] [llvm] [RISCV] Add smstateen extension (PR #90818)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu May 2 08:50:02 PDT 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/90818
>From ef8985a4bb9fe78c273d9d3cb2af17b0d65459c2 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 1 May 2024 20:27:15 -0700
Subject: [PATCH 1/2] [RISCV] Add smstateen extension
---
clang/test/Preprocessor/riscv-target-features.c | 9 +++++++++
llvm/lib/Target/RISCV/RISCVFeatures.td | 3 +++
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++
llvm/test/MC/RISCV/attribute-arch.s | 3 +++
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 +
5 files changed, 20 insertions(+)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index ee4f81cd654bca..913093bb51db6d 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -27,6 +27,7 @@
// CHECK-NOT: __riscv_shvstvecd {{.*$}}
// CHECK-NOT: __riscv_smaia {{.*$}}
// CHECK-NOT: __riscv_smepmp {{.*$}}
+// CHECK-NOT: __riscv_smstateen {{.*$}}
// CHECK-NOT: __riscv_ssaia {{.*$}}
// CHECK-NOT: __riscv_ssccptr {{.*$}}
// CHECK-NOT: __riscv_sscofpmf {{.*$}}
@@ -373,6 +374,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSCOUNTERENW-EXT %s
// CHECK-SSCOUNTERENW-EXT: __riscv_sscounterenw 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ismstateen -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMSTATEEN-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ismstateen -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMSTATEEN-EXT %s
+// CHECK-SMSTATEEN-EXT: __riscv_smstateen 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32issstateen -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSSTATEEN-EXT %s
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index eab1863fdc32ea..a9107a7374d2d9 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -867,6 +867,9 @@ def FeatureStdExtSscounterenw
"'Sscounterenw' (Support writeable scounteren enable "
"bit for any hpmcounter that is not read-only zero)">;
+def FeatureStdExtSmstateen
+ : RISCVExtension<"smstateen", 1, 0,
+ "'Smstateen' (Machine-mode view of the state-enable extension.)">;
def FeatureStdExtSsstateen
: RISCVExtension<"ssstateen", 1, 0,
"'Ssstateen' (Supervisor-mode view of the state-enable extension)">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 7bd3440c9dc0ef..8f49f6648ad281 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -44,6 +44,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCCPTR %s
; RUN: llc -mtriple=riscv32 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCOFPMF %s
; RUN: llc -mtriple=riscv32 -mattr=+sscounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCOUNTERENW %s
+; RUN: llc -mtriple=riscv32 -mattr=+smstateen %s -o - | FileCheck --check-prefixes=CHECK,RV32SMSTATEEN %s
; RUN: llc -mtriple=riscv32 -mattr=+ssstateen %s -o - | FileCheck --check-prefixes=CHECK,RV32SSSTATEEN %s
; RUN: llc -mtriple=riscv32 -mattr=+ssstrict %s -o - | FileCheck --check-prefixes=CHECK,RV32SSSTRICT %s
; RUN: llc -mtriple=riscv32 -mattr=+sstc %s -o - | FileCheck --check-prefixes=CHECK,RV32SSTC %s
@@ -170,6 +171,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCCPTR %s
; RUN: llc -mtriple=riscv64 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCOFPMF %s
; RUN: llc -mtriple=riscv64 -mattr=+sscounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCOUNTERENW %s
+; RUN: llc -mtriple=riscv64 -mattr=+smstateen %s -o - | FileCheck --check-prefixes=CHECK,RV64SMSTATEEN %s
; RUN: llc -mtriple=riscv64 -mattr=+ssstateen %s -o - | FileCheck --check-prefixes=CHECK,RV64SSSTATEEN %s
; RUN: llc -mtriple=riscv64 -mattr=+ssstrict %s -o - | FileCheck --check-prefixes=CHECK,RV64SSSTRICT %s
; RUN: llc -mtriple=riscv64 -mattr=+sstc %s -o - | FileCheck --check-prefixes=CHECK,RV64SSTC %s
@@ -314,6 +316,7 @@
; RV32SSCCPTR: .attribute 5, "rv32i2p1_ssccptr1p0"
; RV32SSCOFPMF: .attribute 5, "rv32i2p1_sscofpmf1p0"
; RV32SSCOUNTERENW: .attribute 5, "rv32i2p1_sscounterenw1p0"
+; RV32SMSTATEEN: .attribute 5, "rv32i2p1_smstateen1p0"
; RV32SSSTATEEN: .attribute 5, "rv32i2p1_ssstateen1p0"
; RV32SSSTRICT: .attribute 5, "rv32i2p1_ssstrict1p0"
; RV32SSTC: .attribute 5, "rv32i2p1_sstc1p0"
@@ -443,6 +446,7 @@
; RV64SSCCPTR: .attribute 5, "rv64i2p1_ssccptr1p0"
; RV64SSCOFPMF: .attribute 5, "rv64i2p1_sscofpmf1p0"
; RV64SSCOUNTERENW: .attribute 5, "rv64i2p1_sscounterenw1p0"
+; RV64SMSTATEEN: .attribute 5, "rv64i2p1_smstateen1p0"
; RV64SSSTATEEN: .attribute 5, "rv64i2p1_ssstateen1p0"
; RV64SSSTRICT: .attribute 5, "rv64i2p1_ssstrict1p0"
; RV64SSTC: .attribute 5, "rv64i2p1_sstc1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index aea27146e37047..a028d4025ec1aa 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -330,6 +330,9 @@
.attribute arch, "rv32i_ssqosid1p0"
# CHECK: attribute 5, "rv32i2p1_ssqosid1p0"
+.attribute arch, "rv32i_smstateen1p0"
+# CHECK: attribute 5, "rv32i2p1_smstateen1p0"
+
.attribute arch, "rv32i_ssstateen1p0"
# CHECK: attribute 5, "rv32i2p1_ssstateen1p0"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 3aa0178100abf4..7167df8531ee05 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -844,6 +844,7 @@ R"(All available -march extensions for RISC-V
shvstvecd 1.0
smaia 1.0
smepmp 1.0
+ smstateen 1.0
ssaia 1.0
ssccptr 1.0
sscofpmf 1.0
>From 7f9fce59a6bd0378a91a3927de04ad4e9a7849a3 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 2 May 2024 08:49:03 -0700
Subject: [PATCH 2/2] fixup! documentation updates
---
llvm/docs/RISCVUsage.rst | 1 +
llvm/docs/ReleaseNotes.rst | 1 +
2 files changed, 2 insertions(+)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index a4cf17a8398a82..ff08c9d345d5f7 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -99,6 +99,7 @@ on support follow.
``Shvstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Smaia`` Supported
``Smepmp`` Supported
+ ``Smstateen`` Assembly Support
``Ssaia`` Supported
``Ssccptr`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Sscofpmf`` Assembly Support
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index d8cc667723f554..d62b2fb3dca9f8 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -119,6 +119,7 @@ Changes to the RISC-V Backend
* Added the CSR names from the Resumable Non-Maskable Interrupts (Smrnmi) extension.
* llvm-objdump now prints disassembled opcode bytes in groups of 2 or 4 bytes to
match GNU objdump. The bytes within the groups are in big endian order.
+* Add smstateen extension to -march. CSR names for smstateen were already supported.
Changes to the WebAssembly Backend
----------------------------------
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