[llvm] SystemZ: Handle gr128 to fp128 copies in copyPhysReg (PR #90861)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/90861

None

>From 00eff166b92452cf00d1f3bd2432d999db216074 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 2 May 2024 16:49:55 +0200
Subject: [PATCH] SystemZ: Handle gr128 to fp128 copies in copyPhysReg

---
 llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp  | 16 ++++
 .../SystemZ/copy-phys-reg-gr128-to-fp128.mir  | 82 +++++++++++++++++++
 2 files changed, 98 insertions(+)
 create mode 100644 llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-fp128.mir

diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index b3517fb0ea77f5..f4e521c824d6e0 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -856,6 +856,22 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     return;
   }
 
+  if (SystemZ::FP128BitRegClass.contains(DestReg) &&
+      SystemZ::GR128BitRegClass.contains(SrcReg)) {
+    MCRegister DestRegHi = RI.getSubReg(DestReg, SystemZ::subreg_h64);
+    MCRegister DestRegLo = RI.getSubReg(DestReg, SystemZ::subreg_l64);
+    MCRegister SrcRegHi = RI.getSubReg(SrcReg, SystemZ::subreg_h64);
+    MCRegister SrcRegLo = RI.getSubReg(SrcReg, SystemZ::subreg_l64);
+
+    BuildMI(MBB, MBBI, DL, get(SystemZ::LDGR), DestRegHi)
+      .addReg(SrcRegHi)
+      .addReg(DestReg, RegState::ImplicitDefine);
+
+    BuildMI(MBB, MBBI, DL, get(SystemZ::LDGR), DestRegLo)
+      .addReg(SrcRegLo, getKillRegState(KillSrc));
+    return;
+  }
+
   // Move CC value from a GR32.
   if (DestReg == SystemZ::CC) {
     unsigned Opcode =
diff --git a/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-fp128.mir b/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-fp128.mir
new file mode 100644
index 00000000000000..d1de915e81cef7
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-fp128.mir
@@ -0,0 +1,82 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -run-pass=postrapseudos -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name:            copy_gr128_to_fp128__r0q_to_f0q
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r0q
+    ; CHECK-LABEL: name: copy_gr128_to_fp128__r0q_to_f0q
+    ; CHECK: liveins: $r0q
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $f0d = LDGR $r0d, implicit-def $f0q
+    ; CHECK-NEXT: $f2d = LDGR $r1d
+    ; CHECK-NEXT: Return implicit $f0q
+    $f0q = COPY $r0q
+    Return implicit $f0q
+...
+
+---
+name:            copy_gr128_to_fp128__r0q_to_f0q_killed
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r0q
+    ; CHECK-LABEL: name: copy_gr128_to_fp128__r0q_to_f0q_killed
+    ; CHECK: liveins: $r0q
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $f0d = LDGR $r0d, implicit-def $f0q
+    ; CHECK-NEXT: $f2d = LDGR killed $r1d
+    ; CHECK-NEXT: Return implicit $f0q
+    $f0q = COPY killed $r0q
+    Return implicit $f0q
+...
+
+---
+name:            copy_gr128_to_fp128__r0q_to_f0q_undef
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r0q
+    ; CHECK-LABEL: name: copy_gr128_to_fp128__r0q_to_f0q_undef
+    ; CHECK: liveins: $r0q
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $f0q = KILL undef $r0q
+    ; CHECK-NEXT: Return implicit $f0q
+    $f0q = COPY undef $r0q
+    Return implicit $f0q
+...
+
+---
+name:            copy_gr128_to_fp128__r0q_to_f0q_subreg0
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r0q
+    ; CHECK-LABEL: name: copy_gr128_to_fp128__r0q_to_f0q_subreg0
+    ; CHECK: liveins: $r0q
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $f0d = LDGR $r0d, implicit-def $f0q
+    ; CHECK-NEXT: $f2d = LDGR $r1d
+    ; CHECK-NEXT: Return implicit $f0q
+    $f0q = COPY $r0q
+    Return implicit $f0q
+...
+
+---
+name:            copy_gr128_to_fp128__r0q_to_f0q_subreg1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r0q
+    ; CHECK-LABEL: name: copy_gr128_to_fp128__r0q_to_f0q_subreg1
+    ; CHECK: liveins: $r0q
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $f0d = LDGR $r0d, implicit-def $f0q
+    ; CHECK-NEXT: $f2d = LDGR $r1d
+    ; CHECK-NEXT: Return implicit $f0q
+    $f0q = COPY $r0q
+    Return implicit $f0q
+...
+