[llvm] [SelectionDAG] Make ARITH_FENCE support half and bfloat type (PR #90836)

[via llvm-commits]

github-actions[bot] wrote:

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:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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git-clang-format --diff a015f015db21e02cbce4ff9d15d0b293e45d0831 065e985f5f3ac4a12f1134fe7d3d6b6573c96003 -- llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 00f94e48a3..362e924d3c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -2826,7 +2826,8 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
                        "result!");
 
   case ISD::ARITH_FENCE:
-    R = SoftPromoteHalfRes_ARITH_FENCE(N); break;
+    R = SoftPromoteHalfRes_ARITH_FENCE(N);
+    break;
   case ISD::BITCAST:    R = SoftPromoteHalfRes_BITCAST(N); break;
   case ISD::ConstantFP: R = SoftPromoteHalfRes_ConstantFP(N); break;
   case ISD::EXTRACT_VECTOR_ELT:

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https://github.com/llvm/llvm-project/pull/90836