[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

================
@@ -1229,14 +1360,18 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
 void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
                                        const MachineInstr &MI) const {
   if (isVectorConfigInstr(MI)) {
-    Info = getInfoForVSETVLI(MI, *MRI);
+    Info = getInfoForVSETVLI(MI, *MRI, LIS);
     return;
   }
 
   if (RISCV::isFaultFirstLoad(MI)) {
     // Update AVL to vl-output of the fault first load.
-    Info.setAVLRegDef(MRI->getVRegDef(MI.getOperand(1).getReg()),
-                      MI.getOperand(1).getReg());
+    if (MI.getOperand(1).getReg() == RISCV::X0)
+      Info.setAVLVLMAX();
----------------
BeMg wrote:

So it could be remain setAVLRegDef after https://github.com/llvm/llvm-project/pull/90636 landed?

```
Info.setAVLRegDef(
    getReachingDefMI(MI.getOperand(1).getReg(), &MI, MRI, LIS),
    MI.getOperand(1).getReg());
```



https://github.com/llvm/llvm-project/pull/70549