[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Luke Lau via llvm-commits]

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@@ -198,13 +231,15 @@ static bool hasUndefinedMergeOp(const MachineInstr &MI,
   if (UseMO.getReg().isPhysical())
     return false;
 
-  if (MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg())) {
+  if (const MachineInstr *UseMI =
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lukel97 wrote:

To clarify, the post-ra LIS path never would have gone past the `if (UseMO.getReg().isPhysical())` statement, because all the vector registers would have been allocated at that point

https://github.com/llvm/llvm-project/pull/70549