[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

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@@ -198,13 +231,15 @@ static bool hasUndefinedMergeOp(const MachineInstr &MI,
   if (UseMO.getReg().isPhysical())
     return false;
 
-  if (MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg())) {
+  if (const MachineInstr *UseMI =
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BeMg wrote:

I don't think it's safe to use getVRegDef to find the register definition here. Even though it's always a virtual register, it's still possible for it to be defined multiple times in non-SSA environment.



https://github.com/llvm/llvm-project/pull/70549