[llvm] [RISCV] Support interleaved accesses for scalable vector. (PR #90583)

[Luke Lau via llvm-commits]

https://github.com/lukel97 approved this pull request.

LGTM, after applying this patch I can see plenty of scalable segmented loads and stores emitted on SPEC CPU 2017 and llvm-test-suite

https://github.com/llvm/llvm-project/pull/90583