[llvm] 0f8d97c - [Hexagon] Fix hexagon-copy-hoisting.mir (#90740)

[via llvm-commits]

Author: Perry MacMurray
Date: 2024-05-01T16:46:41-05:00
New Revision: 0f8d97cccc03246f6b922696b35805c77e022af7

URL: https://github.com/llvm/llvm-project/commit/0f8d97cccc03246f6b922696b35805c77e022af7
DIFF: https://github.com/llvm/llvm-project/commit/0f8d97cccc03246f6b922696b35805c77e022af7.diff

LOG: [Hexagon] Fix hexagon-copy-hoisting.mir (#90740)

The hexagon-copy-hoisting.mir test fails when run with
-verify-machineinstrs. This patch fixes this by disabling
tracksRegLiveness.

Added: 
    

Modified: 
    llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir b/llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir
index 0836cac7f9134f..6f2d562cbe0970 100644
--- a/llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir
+++ b/llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir
@@ -11,7 +11,7 @@
 
 ---
 name:            f0
-tracksRegLiveness: true
+tracksRegLiveness: false
 registers:
   - { id: 0, class: intregs, preferred-register: '' }
   - { id: 1, class: intregs, preferred-register: '' }
@@ -19,15 +19,11 @@ registers:
   - { id: 3, class: predregs, preferred-register: '' }
   - { id: 4, class: intregs, preferred-register: '' }
   - { id: 5, class: intregs, preferred-register: '' }
-liveins:
-  - { reg: '$r0', virtual-reg: '%0' }
-  - { reg: '$r1', virtual-reg: '%1' }
 stack:
   - { id: 0, offset: 0, size: 4, alignment: 8 }
 body: |
   bb.0:
     successors: %bb.1, %bb.2
-    liveins: $r0, $r1
 
     %1:intregs = COPY $r1
     %0:intregs = COPY $r0