[llvm] [InstCombine] Fold adds + shifts with nsw and nuw flags (PR #88193)
via llvm-commits
llvm-commits at lists.llvm.org
Wed May 1 14:15:30 PDT 2024
https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/88193
>From 66fef84ec866b629bea3700d526a11878cb060e2 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Sun, 21 Apr 2024 17:44:48 -0400
Subject: [PATCH 01/12] [InstCombine] Pre-commit tests (NFC)
---
llvm/test/Transforms/InstCombine/ashr-lshr.ll | 48 ++++++++
llvm/test/Transforms/InstCombine/lshr.ll | 104 +++++++++++++++++-
2 files changed, 148 insertions(+), 4 deletions(-)
diff --git a/llvm/test/Transforms/InstCombine/ashr-lshr.ll b/llvm/test/Transforms/InstCombine/ashr-lshr.ll
index ac206dc7999dd2..7dd62327521081 100644
--- a/llvm/test/Transforms/InstCombine/ashr-lshr.ll
+++ b/llvm/test/Transforms/InstCombine/ashr-lshr.ll
@@ -604,3 +604,51 @@ define <2 x i8> @ashr_known_pos_exact_vec(<2 x i8> %x, <2 x i8> %y) {
%r = ashr exact <2 x i8> %p, %y
ret <2 x i8> %r
}
+
+define i32 @ashr_mul_times_3_div_2(i32 %0) {
+; CHECK-LABEL: @ashr_mul_times_3_div_2(
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[TMP0:%.*]], 3
+; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[MUL]], 1
+; CHECK-NEXT: ret i32 [[ASHR]]
+;
+ %mul = mul nsw nuw i32 %0, 3
+ %ashr = ashr i32 %mul, 1
+ ret i32 %ashr
+}
+
+define i32 @ashr_mul_times_3_div_2_exact(i32 %x) {
+; CHECK-LABEL: @ashr_mul_times_3_div_2_exact(
+; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[X:%.*]], 3
+; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i32 [[MUL]], 1
+; CHECK-NEXT: ret i32 [[ASHR]]
+;
+ %mul = mul nsw i32 %x, 3
+ %ashr = ashr exact i32 %mul, 1
+ ret i32 %ashr
+}
+
+define i32 @mul_times_3_div_2_multiuse(i32 %x) {
+; CHECK-LABEL: @mul_times_3_div_2_multiuse(
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[X:%.*]], 3
+; CHECK-NEXT: [[RES:%.*]] = ashr i32 [[MUL]], 1
+; CHECK-NEXT: call void @use(i32 [[MUL]])
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %mul = mul nuw i32 %x, 3
+ %res = ashr i32 %mul, 1
+ call void @use (i32 %mul)
+ ret i32 %res
+}
+
+define i32 @ashr_mul_times_3_div_2_exact_2(i32 %x) {
+; CHECK-LABEL: @ashr_mul_times_3_div_2_exact_2(
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[X:%.*]], 3
+; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i32 [[MUL]], 1
+; CHECK-NEXT: ret i32 [[ASHR]]
+;
+ %mul = mul nuw i32 %x, 3
+ %ashr = ashr exact i32 %mul, 1
+ ret i32 %ashr
+}
+
+declare void @use(i32)
diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index 7d611ba188d6b4..384e6e38b144d2 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -360,7 +360,79 @@ define <3 x i14> @mul_splat_fold_vec(<3 x i14> %x) {
ret <3 x i14> %t
}
-; Negative test
+; Negative tests
+
+define i32 @mul_times_3_div_2(i32 %x) {
+; CHECK-LABEL: @mul_times_3_div_2(
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[X:%.*]], 3
+; CHECK-NEXT: [[RES:%.*]] = lshr i32 [[MUL]], 1
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %mul = mul nsw nuw i32 %x, 3
+ %res = lshr i32 %mul, 1
+ ret i32 %res
+}
+
+define i32 @shl_add_lshr(i32 %x, i32 %c, i32 %y) {
+; CHECK-LABEL: @shl_add_lshr(
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[X:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[SHL]], [[Y:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i32 [[ADD]], [[C]]
+; CHECK-NEXT: ret i32 [[LSHR]]
+;
+ %shl = shl nuw i32 %x, %c
+ %add = add nuw nsw i32 %shl, %y
+ %lshr = lshr exact i32 %add, %c
+ ret i32 %lshr
+}
+
+define i32 @lshr_mul_times_3_div_2_nuw(i32 %0) {
+; CHECK-LABEL: @lshr_mul_times_3_div_2_nuw(
+; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP0:%.*]], 1
+; CHECK-NEXT: [[LSHR:%.*]] = add nuw nsw i32 [[TMP2]], [[TMP0]]
+; CHECK-NEXT: ret i32 [[LSHR]]
+;
+ %mul = mul nuw i32 %0, 3
+ %lshr = lshr i32 %mul, 1
+ ret i32 %lshr
+}
+
+define i32 @lshr_mul_times_3_div_2_nsw(i32 %0) {
+; CHECK-LABEL: @lshr_mul_times_3_div_2_nsw(
+; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP0:%.*]], 3
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[MUL]], 1
+; CHECK-NEXT: ret i32 [[LSHR]]
+;
+ %mul = mul nsw i32 %0, 3
+ %lshr = lshr i32 %mul, 1
+ ret i32 %lshr
+}
+
+; Negative tests
+
+define i32 @mul_times_3_div_2_no_flag(i32 %x) {
+; CHECK-LABEL: @mul_times_3_div_2_no_flag(
+; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 3
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[MUL]], 1
+; CHECK-NEXT: ret i32 [[LSHR]]
+;
+ %mul = mul i32 %x, 3
+ %lshr = lshr i32 %mul, 1
+ ret i32 %lshr
+}
+
+define i32 @shl_add_lshr_neg(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @shl_add_lshr_neg(
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[SHL]], [[Z:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = lshr exact i32 [[ADD]], [[Z]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %shl = shl nuw i32 %x, %y
+ %add = add nuw nsw i32 %shl, %z
+ %res = lshr exact i32 %add, %z
+ ret i32 %res
+}
define i32 @mul_splat_fold_wrong_mul_const(i32 %x) {
; CHECK-LABEL: @mul_splat_fold_wrong_mul_const(
@@ -373,7 +445,33 @@ define i32 @mul_splat_fold_wrong_mul_const(i32 %x) {
ret i32 %t
}
-; Negative test
+define i32 @shl_add_lshr_multiuse(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @shl_add_lshr_multiuse(
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[SHL]], [[Z:%.*]]
+; CHECK-NEXT: call void @use(i32 [[ADD]])
+; CHECK-NEXT: [[RES:%.*]] = lshr exact i32 [[ADD]], [[Z]]
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %shl = shl nuw i32 %x, %y
+ %add = add nuw nsw i32 %shl, %z
+ call void @use (i32 %add)
+ %res = lshr exact i32 %add, %z
+ ret i32 %res
+}
+
+define i32 @mul_times_3_div_2_multiuse(i32 %x) {
+; CHECK-LABEL: @mul_times_3_div_2_multiuse(
+; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[X:%.*]], 3
+; CHECK-NEXT: [[RES:%.*]] = lshr i32 [[MUL]], 1
+; CHECK-NEXT: call void @use(i32 [[MUL]])
+; CHECK-NEXT: ret i32 [[RES]]
+;
+ %mul = mul nuw i32 %x, 3
+ %res = lshr i32 %mul, 1
+ call void @use (i32 %mul)
+ ret i32 %res
+}
define i32 @mul_splat_fold_wrong_lshr_const(i32 %x) {
; CHECK-LABEL: @mul_splat_fold_wrong_lshr_const(
@@ -386,8 +484,6 @@ define i32 @mul_splat_fold_wrong_lshr_const(i32 %x) {
ret i32 %t
}
-; Negative test
-
define i32 @mul_splat_fold_no_nuw(i32 %x) {
; CHECK-LABEL: @mul_splat_fold_no_nuw(
; CHECK-NEXT: [[M:%.*]] = mul nsw i32 [[X:%.*]], 65537
>From 5b3865f9cceabe416230d6042270a7750f9fac85 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Sun, 21 Apr 2024 17:50:52 -0400
Subject: [PATCH 02/12] [InstCombine] Fold adds + shifts with nsw and nuw flags
[InstCombine] Fold adds + shifts with nsw and nuw flags
Proofs:
https://alive2.llvm.org/ce/z/kDVTiL
https://alive2.llvm.org/ce/z/wORNYm
---
.../InstCombine/InstCombineShifts.cpp | 14 +++-
llvm/test/Transforms/InstCombine/ashr-lshr.ll | 48 -------------
llvm/test/Transforms/InstCombine/lshr.ll | 70 +++----------------
3 files changed, 20 insertions(+), 112 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 1cb21a1d81af4b..8272933df272b8 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -1259,6 +1259,18 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
match(Op1, m_SpecificIntAllowPoison(BitWidth - 1)))
return new ZExtInst(Builder.CreateIsNotNeg(X, "isnotneg"), Ty);
+ // If both the add and the shift are nuw, then:
+ // ((X << Z) + Y) nuw >>u Z --> X + (Y >>u Z) nuw
+ Value *Y;
+ if (match(Op0, m_OneUse(m_c_NUWAdd(m_NUWShl(m_Value(X), m_Specific(Op1)),
+ m_Value(Y))))) {
+ Value *NewLshr = Builder.CreateLShr(Y, Op1, "", I.isExact());
+ auto *newAdd = BinaryOperator::CreateNUWAdd(NewLshr, X);
+ if (auto *Op0Bin = cast<OverflowingBinaryOperator>(Op0))
+ newAdd->setHasNoSignedWrap(Op0Bin->hasNoSignedWrap());
+ return newAdd;
+ }
+
if (match(Op1, m_APInt(C))) {
unsigned ShAmtC = C->getZExtValue();
auto *II = dyn_cast<IntrinsicInst>(Op0);
@@ -1275,7 +1287,6 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
return new ZExtInst(Cmp, Ty);
}
- Value *X;
const APInt *C1;
if (match(Op0, m_Shl(m_Value(X), m_APInt(C1))) && C1->ult(BitWidth)) {
if (C1->ult(ShAmtC)) {
@@ -1320,7 +1331,6 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
// ((X << C) + Y) >>u C --> (X + (Y >>u C)) & (-1 >>u C)
// TODO: Consolidate with the more general transform that starts from shl
// (the shifts are in the opposite order).
- Value *Y;
if (match(Op0,
m_OneUse(m_c_Add(m_OneUse(m_Shl(m_Value(X), m_Specific(Op1))),
m_Value(Y))))) {
diff --git a/llvm/test/Transforms/InstCombine/ashr-lshr.ll b/llvm/test/Transforms/InstCombine/ashr-lshr.ll
index 7dd62327521081..ac206dc7999dd2 100644
--- a/llvm/test/Transforms/InstCombine/ashr-lshr.ll
+++ b/llvm/test/Transforms/InstCombine/ashr-lshr.ll
@@ -604,51 +604,3 @@ define <2 x i8> @ashr_known_pos_exact_vec(<2 x i8> %x, <2 x i8> %y) {
%r = ashr exact <2 x i8> %p, %y
ret <2 x i8> %r
}
-
-define i32 @ashr_mul_times_3_div_2(i32 %0) {
-; CHECK-LABEL: @ashr_mul_times_3_div_2(
-; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[TMP0:%.*]], 3
-; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[MUL]], 1
-; CHECK-NEXT: ret i32 [[ASHR]]
-;
- %mul = mul nsw nuw i32 %0, 3
- %ashr = ashr i32 %mul, 1
- ret i32 %ashr
-}
-
-define i32 @ashr_mul_times_3_div_2_exact(i32 %x) {
-; CHECK-LABEL: @ashr_mul_times_3_div_2_exact(
-; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[X:%.*]], 3
-; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i32 [[MUL]], 1
-; CHECK-NEXT: ret i32 [[ASHR]]
-;
- %mul = mul nsw i32 %x, 3
- %ashr = ashr exact i32 %mul, 1
- ret i32 %ashr
-}
-
-define i32 @mul_times_3_div_2_multiuse(i32 %x) {
-; CHECK-LABEL: @mul_times_3_div_2_multiuse(
-; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[X:%.*]], 3
-; CHECK-NEXT: [[RES:%.*]] = ashr i32 [[MUL]], 1
-; CHECK-NEXT: call void @use(i32 [[MUL]])
-; CHECK-NEXT: ret i32 [[RES]]
-;
- %mul = mul nuw i32 %x, 3
- %res = ashr i32 %mul, 1
- call void @use (i32 %mul)
- ret i32 %res
-}
-
-define i32 @ashr_mul_times_3_div_2_exact_2(i32 %x) {
-; CHECK-LABEL: @ashr_mul_times_3_div_2_exact_2(
-; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[X:%.*]], 3
-; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i32 [[MUL]], 1
-; CHECK-NEXT: ret i32 [[ASHR]]
-;
- %mul = mul nuw i32 %x, 3
- %ashr = ashr exact i32 %mul, 1
- ret i32 %ashr
-}
-
-declare void @use(i32)
diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index 384e6e38b144d2..152cf30000c433 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -360,24 +360,12 @@ define <3 x i14> @mul_splat_fold_vec(<3 x i14> %x) {
ret <3 x i14> %t
}
-; Negative tests
-
-define i32 @mul_times_3_div_2(i32 %x) {
-; CHECK-LABEL: @mul_times_3_div_2(
-; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[X:%.*]], 3
-; CHECK-NEXT: [[RES:%.*]] = lshr i32 [[MUL]], 1
-; CHECK-NEXT: ret i32 [[RES]]
-;
- %mul = mul nsw nuw i32 %x, 3
- %res = lshr i32 %mul, 1
- ret i32 %res
-}
+; Negative test
define i32 @shl_add_lshr(i32 %x, i32 %c, i32 %y) {
; CHECK-LABEL: @shl_add_lshr(
-; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[X:%.*]], [[C:%.*]]
-; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[SHL]], [[Y:%.*]]
-; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i32 [[ADD]], [[C]]
+; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[Y:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = add nuw nsw i32 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[LSHR]]
;
%shl = shl nuw i32 %x, %c
@@ -386,40 +374,7 @@ define i32 @shl_add_lshr(i32 %x, i32 %c, i32 %y) {
ret i32 %lshr
}
-define i32 @lshr_mul_times_3_div_2_nuw(i32 %0) {
-; CHECK-LABEL: @lshr_mul_times_3_div_2_nuw(
-; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP0:%.*]], 1
-; CHECK-NEXT: [[LSHR:%.*]] = add nuw nsw i32 [[TMP2]], [[TMP0]]
-; CHECK-NEXT: ret i32 [[LSHR]]
-;
- %mul = mul nuw i32 %0, 3
- %lshr = lshr i32 %mul, 1
- ret i32 %lshr
-}
-
-define i32 @lshr_mul_times_3_div_2_nsw(i32 %0) {
-; CHECK-LABEL: @lshr_mul_times_3_div_2_nsw(
-; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP0:%.*]], 3
-; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[MUL]], 1
-; CHECK-NEXT: ret i32 [[LSHR]]
-;
- %mul = mul nsw i32 %0, 3
- %lshr = lshr i32 %mul, 1
- ret i32 %lshr
-}
-
-; Negative tests
-
-define i32 @mul_times_3_div_2_no_flag(i32 %x) {
-; CHECK-LABEL: @mul_times_3_div_2_no_flag(
-; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 3
-; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[MUL]], 1
-; CHECK-NEXT: ret i32 [[LSHR]]
-;
- %mul = mul i32 %x, 3
- %lshr = lshr i32 %mul, 1
- ret i32 %lshr
-}
+; Negative test
define i32 @shl_add_lshr_neg(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @shl_add_lshr_neg(
@@ -445,6 +400,8 @@ define i32 @mul_splat_fold_wrong_mul_const(i32 %x) {
ret i32 %t
}
+; Negative test
+
define i32 @shl_add_lshr_multiuse(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @shl_add_lshr_multiuse(
; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[X:%.*]], [[Y:%.*]]
@@ -460,19 +417,6 @@ define i32 @shl_add_lshr_multiuse(i32 %x, i32 %y, i32 %z) {
ret i32 %res
}
-define i32 @mul_times_3_div_2_multiuse(i32 %x) {
-; CHECK-LABEL: @mul_times_3_div_2_multiuse(
-; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[X:%.*]], 3
-; CHECK-NEXT: [[RES:%.*]] = lshr i32 [[MUL]], 1
-; CHECK-NEXT: call void @use(i32 [[MUL]])
-; CHECK-NEXT: ret i32 [[RES]]
-;
- %mul = mul nuw i32 %x, 3
- %res = lshr i32 %mul, 1
- call void @use (i32 %mul)
- ret i32 %res
-}
-
define i32 @mul_splat_fold_wrong_lshr_const(i32 %x) {
; CHECK-LABEL: @mul_splat_fold_wrong_lshr_const(
; CHECK-NEXT: [[M:%.*]] = mul nuw i32 [[X:%.*]], 65537
@@ -484,6 +428,8 @@ define i32 @mul_splat_fold_wrong_lshr_const(i32 %x) {
ret i32 %t
}
+; Negative test
+
define i32 @mul_splat_fold_no_nuw(i32 %x) {
; CHECK-LABEL: @mul_splat_fold_no_nuw(
; CHECK-NEXT: [[M:%.*]] = mul nsw i32 [[X:%.*]], 65537
>From fc578eac96d1cf0c068126a561bb6d734e7c1ad5 Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Wed, 1 May 2024 09:03:18 -0400
Subject: [PATCH 03/12] Update lshr.ll
---
llvm/test/Transforms/InstCombine/lshr.ll | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index 152cf30000c433..4f6867998fbaa0 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -360,8 +360,6 @@ define <3 x i14> @mul_splat_fold_vec(<3 x i14> %x) {
ret <3 x i14> %t
}
-; Negative test
-
define i32 @shl_add_lshr(i32 %x, i32 %c, i32 %y) {
; CHECK-LABEL: @shl_add_lshr(
; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[Y:%.*]], [[C:%.*]]
>From 8f9435700c993546a7c039b4db7cda120931c16e Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Wed, 1 May 2024 10:19:23 -0400
Subject: [PATCH 04/12] Update InstCombineShifts.cpp
Co-authored-by: Yingwei Zheng <dtcxzyw at qq.com>
---
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 8272933df272b8..570dd9a2c120bf 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -1265,7 +1265,7 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
if (match(Op0, m_OneUse(m_c_NUWAdd(m_NUWShl(m_Value(X), m_Specific(Op1)),
m_Value(Y))))) {
Value *NewLshr = Builder.CreateLShr(Y, Op1, "", I.isExact());
- auto *newAdd = BinaryOperator::CreateNUWAdd(NewLshr, X);
+ auto *NewAdd = BinaryOperator::CreateNUWAdd(NewLshr, X);
if (auto *Op0Bin = cast<OverflowingBinaryOperator>(Op0))
newAdd->setHasNoSignedWrap(Op0Bin->hasNoSignedWrap());
return newAdd;
>From 3ccd398d661d853f6b74b9f320c50782dde1a1fc Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Wed, 1 May 2024 10:19:32 -0400
Subject: [PATCH 05/12] Update InstCombineShifts.cpp
Co-authored-by: Yingwei Zheng <dtcxzyw at qq.com>
---
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 570dd9a2c120bf..0fde03899c1ace 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -1266,8 +1266,7 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
m_Value(Y))))) {
Value *NewLshr = Builder.CreateLShr(Y, Op1, "", I.isExact());
auto *NewAdd = BinaryOperator::CreateNUWAdd(NewLshr, X);
- if (auto *Op0Bin = cast<OverflowingBinaryOperator>(Op0))
- newAdd->setHasNoSignedWrap(Op0Bin->hasNoSignedWrap());
+ newAdd->setHasNoSignedWrap(cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap());
return newAdd;
}
>From ec5f2c9620bcf329957debe3bb1cbf2a7c2a4c4f Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Wed, 1 May 2024 10:19:42 -0400
Subject: [PATCH 06/12] Update InstCombineShifts.cpp
Co-authored-by: Yingwei Zheng <dtcxzyw at qq.com>
---
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 0fde03899c1ace..0c2a333bb9115a 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -1260,7 +1260,7 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
return new ZExtInst(Builder.CreateIsNotNeg(X, "isnotneg"), Ty);
// If both the add and the shift are nuw, then:
- // ((X << Z) + Y) nuw >>u Z --> X + (Y >>u Z) nuw
+ // ((X <<nuw Z) +nuw Y) >>u Z --> X +nuw (Y >>u Z)
Value *Y;
if (match(Op0, m_OneUse(m_c_NUWAdd(m_NUWShl(m_Value(X), m_Specific(Op1)),
m_Value(Y))))) {
>From fa1739c86d04846d0a19b65b3991774fd177d3e0 Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Wed, 1 May 2024 12:34:39 -0400
Subject: [PATCH 07/12] Update InstCombineShifts.cpp
---
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 0c2a333bb9115a..7ee031dcbfe7dd 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -1266,8 +1266,8 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
m_Value(Y))))) {
Value *NewLshr = Builder.CreateLShr(Y, Op1, "", I.isExact());
auto *NewAdd = BinaryOperator::CreateNUWAdd(NewLshr, X);
- newAdd->setHasNoSignedWrap(cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap());
- return newAdd;
+ NewAdd->setHasNoSignedWrap(cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap());
+ return NewAdd;
}
if (match(Op1, m_APInt(C))) {
>From 9db759c3b9b53f8582c22fec66f8e741dc470a17 Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Wed, 1 May 2024 12:35:30 -0400
Subject: [PATCH 08/12] Update InstCombineShifts.cpp
---
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 7ee031dcbfe7dd..8538d261c900e7 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -1266,7 +1266,7 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
m_Value(Y))))) {
Value *NewLshr = Builder.CreateLShr(Y, Op1, "", I.isExact());
auto *NewAdd = BinaryOperator::CreateNUWAdd(NewLshr, X);
- NewAdd->setHasNoSignedWrap(cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap());
+ NewAdd->setHasNoSignedWrap(cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap());
return NewAdd;
}
>From d60558eab59c524f2e18624c43a4ceb9d7900f04 Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Wed, 1 May 2024 12:39:25 -0400
Subject: [PATCH 09/12] Update InstCombineShifts.cpp
---
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 8538d261c900e7..62add12ac63b77 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -1266,7 +1266,8 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
m_Value(Y))))) {
Value *NewLshr = Builder.CreateLShr(Y, Op1, "", I.isExact());
auto *NewAdd = BinaryOperator::CreateNUWAdd(NewLshr, X);
- NewAdd->setHasNoSignedWrap(cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap());
+ NewAdd->setHasNoSignedWrap(
+ cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap());
return NewAdd;
}
>From e2fdf04c4973c4773fef2e01d9c11dae0d8c059f Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Wed, 1 May 2024 17:09:36 -0400
Subject: [PATCH 10/12] Update InstCombineShifts.cpp
---
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 62add12ac63b77..588ea24fb3cb56 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -1267,7 +1267,7 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
Value *NewLshr = Builder.CreateLShr(Y, Op1, "", I.isExact());
auto *NewAdd = BinaryOperator::CreateNUWAdd(NewLshr, X);
NewAdd->setHasNoSignedWrap(
- cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap());
+ cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap());
return NewAdd;
}
>From 95d34ded8fa9b8a13c9c2f95fd9f50ced94c5e54 Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Wed, 1 May 2024 17:13:49 -0400
Subject: [PATCH 11/12] Add requested changes
---
llvm/test/Transforms/InstCombine/lshr.ll | 30 ++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index 4f6867998fbaa0..cf065fc7ae78b8 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -360,8 +360,8 @@ define <3 x i14> @mul_splat_fold_vec(<3 x i14> %x) {
ret <3 x i14> %t
}
-define i32 @shl_add_lshr(i32 %x, i32 %c, i32 %y) {
-; CHECK-LABEL: @shl_add_lshr(
+define i32 @shl_add_lshr_flag_preservation(i32 %x, i32 %c, i32 %y) {
+; CHECK-LABEL: @shl_add_lshr_flag_preservation(
; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[Y:%.*]], [[C:%.*]]
; CHECK-NEXT: [[LSHR:%.*]] = add nuw nsw i32 [[TMP1]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[LSHR]]
@@ -372,6 +372,32 @@ define i32 @shl_add_lshr(i32 %x, i32 %c, i32 %y) {
ret i32 %lshr
}
+
+define i32 @shl_add_lshr(i32 %x, i32 %c, i32 %y) {
+; CHECK-LABEL: @shl_add_lshr(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[Y:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = add nuw i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[LSHR]]
+;
+ %shl = shl nuw i32 %x, %c
+ %add = add nuw i32 %shl, %y
+ %lshr = lshr i32 %add, %c
+ ret i32 %lshr
+}
+
+define i32 @shl_add_lshr_comm(i32 %x, i32 %c, i32 %y) {
+; CHECK-LABEL: @shl_add_lshr_comm(
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[Y:%.*]], [[C:%.*]]
+; CHECK-NEXT: [[LSHR:%.*]] = add nuw i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT: ret i32 [[LSHR]]
+;
+ %shl = shl nuw i32 %x, %c
+ %add = add nuw i32 %y, %shl
+ %lshr = lshr i32 %add, %c
+ ret i32 %lshr
+}
+
+
; Negative test
define i32 @shl_add_lshr_neg(i32 %x, i32 %y, i32 %z) {
>From 1e7783d4dfde8d270da5c5da65bf1e9f2d4266ec Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Wed, 1 May 2024 17:15:16 -0400
Subject: [PATCH 12/12] Formatting
---
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 588ea24fb3cb56..28c456140961e7 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -1260,7 +1260,7 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
return new ZExtInst(Builder.CreateIsNotNeg(X, "isnotneg"), Ty);
// If both the add and the shift are nuw, then:
- // ((X <<nuw Z) +nuw Y) >>u Z --> X +nuw (Y >>u Z)
+ // ((X << nuw Z) + nuw Y) >>u Z --> X + nuw (Y >>u Z)
Value *Y;
if (match(Op0, m_OneUse(m_c_NUWAdd(m_NUWShl(m_Value(X), m_Specific(Op1)),
m_Value(Y))))) {
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