[llvm] promote Pseduo Opcode from 32bit to 64bits after eliminating the `extsw` instruction in PPCMIPeepholes optimization (PR #85451)
zhijian lin via llvm-commits
llvm-commits at lists.llvm.org
Wed May 1 14:04:58 PDT 2024
================
@@ -5234,6 +5234,218 @@ bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
// We limit the max depth to track incoming values of PHIs or binary ops
// (e.g. AND) to avoid excessive cost.
const unsigned MAX_BINOP_DEPTH = 1;
+
+void PPCInstrInfo::replaceInstrAfterElimExt32To64(const Register &Reg,
+ MachineRegisterInfo *MRI,
+ unsigned BinOpDepth,
+ LiveVariables *LV) const {
+ MachineInstr *MI = MRI->getVRegDef(Reg);
+ if (!MI)
+ return;
+
+ unsigned Opcode = MI->getOpcode();
+ bool IsReplaceInstr = false;
+ int NewOpcode = -1;
+
+ auto SetNewOpcode = [&](int NewOpc) {
+ if (!IsReplaceInstr) {
+ NewOpcode = NewOpc;
+ IsReplaceInstr = true;
+ }
+ };
+
+ switch (Opcode) {
+ case PPC::OR:
+ SetNewOpcode(PPC::OR8);
+ [[fallthrough]];
+ case PPC::ISEL:
+ SetNewOpcode(PPC::ISEL8);
+ [[fallthrough]];
+ case PPC::OR8:
+ case PPC::PHI:
+ if (BinOpDepth < MAX_BINOP_DEPTH) {
+ unsigned OperandEnd = 3, OperandStride = 1;
+ if (Opcode == PPC::PHI) {
+ OperandEnd = MI->getNumOperands();
+ OperandStride = 2;
+ }
+
+ for (unsigned I = 1; I != OperandEnd; I += OperandStride) {
+ assert(MI->getOperand(I).isReg() && "Operand must be register");
+ Register SrcReg = MI->getOperand(I).getReg();
+ replaceInstrAfterElimExt32To64(SrcReg, MRI, BinOpDepth + 1, LV);
+ }
+
+ if (!IsReplaceInstr)
+ return;
+ }
+ break;
+ case PPC::COPY: {
+ Register SrcReg = MI->getOperand(1).getReg();
+ const MachineFunction *MF = MI->getMF();
+ if (!MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
+ replaceInstrAfterElimExt32To64(SrcReg, MRI, BinOpDepth, LV);
+ return;
+ }
+ // From here on everything is SVR4ABI
+ if (MI->getParent()->getBasicBlock() == &MF->getFunction().getEntryBlock())
+ return;
+
+ if (SrcReg != PPC::X3) {
+ replaceInstrAfterElimExt32To64(SrcReg, MRI, BinOpDepth, LV);
+ return;
+ }
+ }
+ return;
+ case PPC::ORI:
+ SetNewOpcode(PPC::ORI8);
+ [[fallthrough]];
+ case PPC::XORI:
+ SetNewOpcode(PPC::XORI8);
+ [[fallthrough]];
+ case PPC::ORIS:
+ SetNewOpcode(PPC::ORIS8);
+ [[fallthrough]];
+ case PPC::XORIS:
+ SetNewOpcode(PPC::XORIS8);
+ [[fallthrough]];
+ case PPC::ORI8:
+ case PPC::XORI8:
+ case PPC::ORIS8:
+ case PPC::XORIS8: {
+ Register SrcReg = MI->getOperand(1).getReg();
+ replaceInstrAfterElimExt32To64(SrcReg, MRI, BinOpDepth, LV);
+
+ if (!IsReplaceInstr)
+ return;
+ break;
+ }
+ case PPC::AND:
+ SetNewOpcode(PPC::AND8);
+ [[fallthrough]];
+ case PPC::AND8: {
+ if (BinOpDepth < MAX_BINOP_DEPTH) {
+ Register SrcReg1 = MI->getOperand(1).getReg();
+ replaceInstrAfterElimExt32To64(SrcReg1, MRI, BinOpDepth, LV);
+ Register SrcReg2 = MI->getOperand(2).getReg();
+ replaceInstrAfterElimExt32To64(SrcReg2, MRI, BinOpDepth, LV);
+ if (!IsReplaceInstr)
+ return;
+ }
+ break;
+ }
+ case PPC::RLWINM:
+ SetNewOpcode(PPC::RLWINM8);
+ break;
+ case PPC::RLWINM_rec:
+ SetNewOpcode(PPC::RLWINM8_rec);
+ break;
+ case PPC::RLWNM:
+ SetNewOpcode(PPC ::RLWNM8);
+ break;
+ case PPC::RLWNM_rec:
+ SetNewOpcode(PPC::RLWNM8_rec);
+ break;
+ case PPC::ANDC_rec:
+ SetNewOpcode(PPC::ANDC8_rec);
+ break;
+ case PPC::ANDIS_rec:
+ SetNewOpcode(PPC::ANDIS8_rec);
+ break;
+ default:
+ break;
+ }
+
----------------
diggerlin wrote:
I double check , if I pull the code , it will change the logic.
https://github.com/llvm/llvm-project/pull/85451
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