[llvm] promote Pseduo Opcode from 32bit to 64bits after eliminating the `extsw` instruction in PPCMIPeepholes optimization (PR #85451)

[zhijian lin via llvm-commits]

================
@@ -525,6 +525,18 @@ def getAltVSXFMAOpcode : InstrMapping {
   let ValueCols = [["1"]];
 }
 
+def get64BitInstrFromSignedExt32BitInstr : InstrMapping {
+  let FilterClass = "SExt32To64";
+  // Instructions with the same opcode.
+  let RowFields = ["Inst"];
+  // Instructions with the same Interpretation64Bit value form a column.
----------------
diggerlin wrote:

> _let FilterClass = "SExt32To64"_

means we will deal with the instruction which only has flag `SExt32To64`

> let RowFields = ["Inst"];

means that if two instruction has the same Pseduo Opcode will be on the same row.

> let ColFields = ["Interpretation64Bit"];

means that the instruction for 64bit is one column, 32-bit is another column.

it will generate something like this 
```
int get64BitInstrFromSignedExt32BitInstr(uint16_t Opcode) {
static const uint16_t get64BitInstrFromSignedExt32BitInstrTable[][2] = {
  { PPC::ANDI_rec, PPC::ANDI8_rec },
  { PPC::EXTSB, PPC::EXTSB8 },
  { PPC::EXTSB8_32_64, PPC::EXTSB8 },
  { PPC::EXTSB_rec, PPC::EXTSB8_rec },
  { PPC::EXTSH, PPC::EXTSH8 },
  { PPC::EXTSH8_32_64, PPC::EXTSH8 },
  { PPC::EXTSH_rec, PPC::EXTSH8_rec },
  { PPC::EXTSW, PPC::EXTSW_32_64 },
  { PPC::EXTSW_rec, PPC::EXTSW_32_64_rec },
  { PPC::LBZ, PPC::LBZ8 },
  { PPC::LBZX, PPC::LBZX8 },
  { PPC::LHA, PPC::LHA8 },
  { PPC::LHAX, PPC::LHAX8 },
  { PPC::LHZ, PPC::LHZ8 },
  { PPC::LHZX, PPC::LHZX8 },
  { PPC::LI, PPC::LI8 },
```

https://github.com/llvm/llvm-project/pull/85451