[llvm] [AMDGPU] New intrinsic llvm.amdgcn.pops.exiting.wave.id (PR #89612)

[Jay Foad via llvm-commits]

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@@ -213,6 +213,11 @@ let isMoveImm = 1 in {
   } // End Uses = [SCC]
 } // End isMoveImm = 1
 
+// Variant of S_MOV_B32 used for reading volatile source values like
+// SRC_POPS_EXITING_WAVE_ID.
+let mayLoad = 1, mayStore = 1, maybeAtomic = 0 in
+def S_MOV_B32_loadstore : SOP1_32 <"s_mov_b32">;
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jayfoad wrote:

I have not yet managed to prevent TableGen from complaining about selecting an IntrInaccessibleMemOnly intrinsic to an instruction without mayLoad/mayStore. The flag inference stuff in CodeGenDAGPatterns::InferFromPattern is just too complex.

https://github.com/llvm/llvm-project/pull/89612