[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Sander de Smalen via llvm-commits]

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@@ -3287,8 +3351,39 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
           !RegInfo->isReservedReg(MF, PairedReg))
         ExtraCSSpill = PairedReg;
     }
+
+    // Save PReg in FunctionInfo to build PTRUE instruction later. The PTRUE is
+    // being used in the function to save and restore the pair of ZReg
+    AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
+    if (Subtarget.hasSVE2p1() || Subtarget.hasSME2()) {
+      if (AArch64::PPRRegClass.contains(Reg) &&
+          (Reg >= AArch64::P8 && Reg <= AArch64::P15) && SavedRegs.test(Reg) &&
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sdesmalen-arm wrote:

When choosing a callee-saved register, there is the assumption that in the prologue this register will already be spilled *before* overwriting it with a new `ptrue`, and in the epilogue that it will be filled *after* defining it with a `ptrue`. This is dependent on the order in which the registers are specified in the AArch64CallingConvention.td file and the order in which they are iterated. To avoid this ever silently doing the wrong thing, can you add some asserts in `restoreCalleeSavedRegisters` and `spillCalleeSavedRegisters` to guard that?

https://github.com/llvm/llvm-project/pull/77665