[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Sander de Smalen via llvm-commits]

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@@ -3187,15 +3224,41 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
       std::swap(Reg1, Reg2);
       std::swap(FrameIdxReg1, FrameIdxReg2);
     }
-    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII.get(LdrOpc));
-    if (RPI.isPaired()) {
-      MIB.addReg(Reg2, getDefRegState(true));
+
+    AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
+    if (RPI.isPaired() && RPI.isScalable()) {
+      unsigned PnReg = AFI->getPredicateRegForFillSpill();
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sdesmalen-arm wrote:

This code now assumes that this predicate is non-zero and that SVE2p1 or SME2 is available, when it finds a paired scalable vector. Can you add some asserts to guard this?

https://github.com/llvm/llvm-project/pull/77665