[llvm] SystemZ: Add missing predicate for bitconvert patterns (PR #90715)
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Wed May 1 02:33:27 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-systemz
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
This will prevent accidentally mis-selecting some conversions on targets without vector registers.
---
Full diff: https://github.com/llvm/llvm-project/pull/90715.diff
1 Files Affected:
- (modified) llvm/lib/Target/SystemZ/SystemZInstrVector.td (+2)
``````````diff
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrVector.td b/llvm/lib/Target/SystemZ/SystemZInstrVector.td
index c29c54a6cb79de..c09f48891c1391 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrVector.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrVector.td
@@ -1692,6 +1692,7 @@ let Predicates = [FeatureVector] in
// Conversions
//===----------------------------------------------------------------------===//
+let Predicates = [FeatureVector] in {
def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
@@ -1755,6 +1756,7 @@ def : Pat<(i128 (bitconvert (v2i64 VR128:$src))), (i128 VR128:$src)>;
def : Pat<(i128 (bitconvert (v4f32 VR128:$src))), (i128 VR128:$src)>;
def : Pat<(i128 (bitconvert (v2f64 VR128:$src))), (i128 VR128:$src)>;
def : Pat<(i128 (bitconvert (f128 VR128:$src))), (i128 VR128:$src)>;
+} // End Predicates = [FeatureVector]
//===----------------------------------------------------------------------===//
// Replicating scalars
``````````
</details>
https://github.com/llvm/llvm-project/pull/90715
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