[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Luke Lau via llvm-commits]

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@@ -1229,14 +1360,18 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
 void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
                                        const MachineInstr &MI) const {
   if (isVectorConfigInstr(MI)) {
-    Info = getInfoForVSETVLI(MI, *MRI);
+    Info = getInfoForVSETVLI(MI, *MRI, LIS);
     return;
   }
 
   if (RISCV::isFaultFirstLoad(MI)) {
     // Update AVL to vl-output of the fault first load.
-    Info.setAVLRegDef(MRI->getVRegDef(MI.getOperand(1).getReg()),
-                      MI.getOperand(1).getReg());
+    if (MI.getOperand(1).getReg() == RISCV::X0)
+      Info.setAVLVLMAX();
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lukel97 wrote:

This is the output VL, not the AVL. If it's set to X0 then I think we lose the information about what VL might be after the vleff. That's part of the reason why it would be easier to defer RISCVDeadRegisterDefinitions till after vsetvli insertion

https://github.com/llvm/llvm-project/pull/70549