[llvm] [RISCV] Optimize pattern `(setcc (selectLT (vfirst_vl ...) , 0, EVL, ...), EVL)` (PR #90538)

[Craig Topper via llvm-commits]

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@@ -13678,9 +13687,79 @@ static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
                                    const RISCVSubtarget &Subtarget) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
+  ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
   EVT VT = N->getValueType(0);
   EVT OpVT = N0.getValueType();
+  SDLoc DL(N);
+
+  // Both rules are looking for an equality compare.
+  if (!isIntEqualitySetCC(Cond))
+    return SDValue();
+
+  // Rule 1
+  using namespace SDPatternMatch;
+  auto matchSelectCC = [](SDValue Op, SDValue VLCandidate, bool Inverse,
+                          SDValue &Select) -> bool {
+    SDValue VFirst, CC;
+    // FIXME: These pattern will fail to match if VFIRST_VL is coming from
+    // a llvm.vp.cttz.elts that doesn't return XLen type. Due to non-trivial
+    // number of sext(_inreg) and zext interleaving between the nodes.
+    // That said, this is not really problem as long as we always generate the
+    // said intrinsics with XLen return type.
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topperc wrote:

The vectorizer will very likely use i32 not XLen.

https://github.com/llvm/llvm-project/pull/90538