[llvm] [SelectionDAG][X86] Add a NoWrap flag to SelectionDAG::isAddLike. NFC (PR #90681)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

If this flag is set, Xor will not be considered AddLike. If the Xor were treated as an Add it may wrap. If we can prove there would be no carry, the Xor would be turned into a disjoint Or by DAGCombine.

Use this to fix a bug in X86 where an Xor is incorrectly being treated as an NUWAdd.

Fixes #<!-- -->90668.

---
Full diff: https://github.com/llvm/llvm-project/pull/90681.diff


4 Files Affected:

- (modified) llvm/include/llvm/CodeGen/SelectionDAG.h (+3-2) 
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+2-2) 
- (modified) llvm/lib/Target/X86/X86ISelDAGToDAG.cpp (+1-1) 
- (modified) llvm/test/CodeGen/X86/pr90668.ll (+2-1) 


``````````diff
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index f353aef1f446ff..4b1b58d4af0bb7 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -2083,8 +2083,9 @@ class SelectionDAG {
   /// Return true if the specified operand is an ISD::OR or ISD::XOR node
   /// that can be treated as an ISD::ADD node.
   /// or(x,y) == add(x,y) iff haveNoCommonBitsSet(x,y)
-  /// xor(x,y) == add(x,y) iff isMinSignedConstant(y)
-  bool isADDLike(SDValue Op) const;
+  /// xor(x,y) == add(x,y) iff isMinSignedConstant(y) && !NoWrap
+  /// If \p NoWrap is true, this will not match ISD::XOR.
+  bool isADDLike(SDValue Op, bool NoWrap = false) const;
 
   /// Return true if the specified operand is an ISD::ADD with a ConstantSDNode
   /// on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index dfbfaa8c894f55..d92976bc2f300a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5231,13 +5231,13 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
   return true;
 }
 
-bool SelectionDAG::isADDLike(SDValue Op) const {
+bool SelectionDAG::isADDLike(SDValue Op, bool NoWrap) const {
   unsigned Opcode = Op.getOpcode();
   if (Opcode == ISD::OR)
     return Op->getFlags().hasDisjoint() ||
            haveNoCommonBitsSet(Op.getOperand(0), Op.getOperand(1));
   if (Opcode == ISD::XOR)
-    return isMinSignedConstant(Op.getOperand(1));
+    return !NoWrap && isMinSignedConstant(Op.getOperand(1));
   return false;
 }
 
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 0e89371f2f1d27..14c62893766ad5 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2353,7 +2353,7 @@ SDValue X86DAGToDAGISel::matchIndexRecursively(SDValue N,
     SDValue Src = N.getOperand(0);
     unsigned SrcOpc = Src.getOpcode();
     if (((SrcOpc == ISD::ADD && Src->getFlags().hasNoUnsignedWrap()) ||
-         CurDAG->isADDLike(Src)) &&
+         CurDAG->isADDLike(Src, /*NoWrap=*/true)) &&
         Src.hasOneUse()) {
       if (CurDAG->isBaseWithConstantOffset(Src)) {
         SDValue AddSrc = Src.getOperand(0);
diff --git a/llvm/test/CodeGen/X86/pr90668.ll b/llvm/test/CodeGen/X86/pr90668.ll
index 28c016ce28aad4..e3aa638b850f25 100644
--- a/llvm/test/CodeGen/X86/pr90668.ll
+++ b/llvm/test/CodeGen/X86/pr90668.ll
@@ -4,8 +4,9 @@
 define i64 @off(i8 signext %a) {
 ; CHECK-LABEL: off:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addb $-128, %dil
 ; CHECK-NEXT:    movzbl %dil, %eax
-; CHECK-NEXT:    leal 1024(,%rax,8), %eax
+; CHECK-NEXT:    shll $3, %eax
 ; CHECK-NEXT:    retq
 entry:
   %add = xor i8 %a, -128

``````````

</details>


https://github.com/llvm/llvm-project/pull/90681