[llvm] 9b07a03 - [Hexagon] Let ArrayRef infer the array size (NFC) (#90534)

via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 30 12:21:33 PDT 2024


Author: Kazu Hirata
Date: 2024-04-30T12:21:29-07:00
New Revision: 9b07a035f1802e826d2186eae1875d010048618a

URL: https://github.com/llvm/llvm-project/commit/9b07a035f1802e826d2186eae1875d010048618a
DIFF: https://github.com/llvm/llvm-project/commit/9b07a035f1802e826d2186eae1875d010048618a.diff

LOG: [Hexagon] Let ArrayRef infer the array size (NFC) (#90534)

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 6b0315bc1befaa..31e37dcce415f1 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1006,8 +1006,7 @@ bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI,
 
   static const Register Regs01[] = { LC0, SA0, LC1, SA1 };
   static const Register Regs1[]  = { LC1, SA1 };
-  auto CheckRegs = IsInnerHWLoop ? ArrayRef(Regs01, std::size(Regs01))
-                                 : ArrayRef(Regs1, std::size(Regs1));
+  auto CheckRegs = IsInnerHWLoop ? ArrayRef(Regs01) : ArrayRef(Regs1);
   for (Register R : CheckRegs)
     if (MI->modifiesRegister(R, TRI))
       return true;


        


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