[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Luke Lau via llvm-commits]

================
@@ -1705,11 +1875,16 @@ void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
     MachineInstr &MI = *I++;
     if (RISCV::isFaultFirstLoad(MI)) {
       Register VLOutput = MI.getOperand(1).getReg();
-      if (!MRI->use_nodbg_empty(VLOutput))
-        BuildMI(MBB, I, MI.getDebugLoc(), TII->get(RISCV::PseudoReadVL),
-                VLOutput);
+      bool IsVirtual = MI.getOperand(1).getReg().isVirtual();
----------------
lukel97 wrote:

Ah it is actually coming from RISCVDeadRegisterDefinitions, but only once we do vsetvl insertion post regalloc.

I think we will probably want to move that to post reg alloc since it looks like it actually catches a few vsetvli cases, where we can't tell the VL def is dead until phi elimination. I'll try and create a PR for that.

https://github.com/llvm/llvm-project/pull/70549