[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Luke Lau via llvm-commits]

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@@ -1705,11 +1875,16 @@ void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
     MachineInstr &MI = *I++;
     if (RISCV::isFaultFirstLoad(MI)) {
       Register VLOutput = MI.getOperand(1).getReg();
-      if (!MRI->use_nodbg_empty(VLOutput))
-        BuildMI(MBB, I, MI.getDebugLoc(), TII->get(RISCV::PseudoReadVL),
-                VLOutput);
+      bool IsVirtual = MI.getOperand(1).getReg().isVirtual();
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lukel97 wrote:

Looks like it's coming from RISCVDeadRegisterDefinitions, I wonder if we can just run move that to post reg alloc too.

https://github.com/llvm/llvm-project/pull/70549