[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 30 05:19:31 PDT 2024
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@@ -198,13 +231,15 @@ static bool hasUndefinedMergeOp(const MachineInstr &MI,
if (UseMO.getReg().isPhysical())
return false;
- if (MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg())) {
+ if (const MachineInstr *UseMI =
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lukel97 wrote:
If we get here it will always be a virtual register so I think we can keep the old version and just use `MRI.getVRegDef(UseMO.getReg())`?
https://github.com/llvm/llvm-project/pull/70549
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