[llvm] [RISCV] Run DeadMachineInstructionElim after regalloc (PR #90598)

[Yingwei Zheng via llvm-commits]

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@@ -553,6 +553,8 @@ void RISCVPassConfig::addPostRegAlloc() {
   if (TM->getOptLevel() != CodeGenOptLevel::None &&
       EnableRedundantCopyElimination)
     addPass(createRISCVRedundantCopyEliminationPass());
+  // RISCVInsertVSETVLI may leave some defs of AVLs dead, so remove them.
+  addPass(&DeadMachineInstructionElimID);
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dtcxzyw wrote:

Please update O3-pipeline.ll

https://github.com/llvm/llvm-project/pull/90598