[llvm] [SelectionDAG][RISCV] Move VP_REDUCE* legalization to LegalizeDAG.cpp. (PR #90522)

[Craig Topper via llvm-commits]

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@@ -5613,6 +5668,13 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
                     DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)));
     break;
   }
+  case ISD::VP_REDUCE_FADD:
+  case ISD::VP_REDUCE_FMUL:
+  case ISD::VP_REDUCE_FMAX:
+  case ISD::VP_REDUCE_FMIN:
+  case ISD::VP_REDUCE_SEQ_FADD:
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topperc wrote:

I removed them because they weren't tested. The code was incorrect as written for min/max because it promoted using any_extend instead of sign/zero_extend. I can add it back and fix the bugs if you think I should. The function was introduced specifically for f16 on RISC-V.

https://github.com/llvm/llvm-project/pull/90522