[llvm] Riscv branch peephole opt (PR #90451)

[Zhijin Zeng via llvm-commits]

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@@ -0,0 +1,121 @@
+//===- RISCVMIPeepholeOpt.cpp - RISC-V MI peephole optimization pass ---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass performs below peephole optimizations on MIR level.
+//
+// 1. Remove redundant branch instrunctions which may be generated by
+// block-placement.
+//
+//    bne a1, a1, %bb.1
+//    blt a1, a1, %bb.1
+//    bltu a1, a1, %bb.1
+//
+//    These instruction is bound to fallthrough to next basic block, rather
+//    than into the %bb.1, so it should be removed here.
+//
+// 2. beq a1, a1, %bb.1 -> j %bb.1
+//    bge a1, a1, %bb.1 -> j %bb.1
+//    bgeu a1, a1, %bb.1 -> j %bb.1
+//
+//    These instruction is bound to go into %bb.1, so it should be replaced by
+//    j pseudo instruction.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCVInstrInfo.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveIntervals.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/Debug.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-mi-peephole-opt"
+
+namespace {
+
+struct RISCVMIPeepholeOpt : public MachineFunctionPass {
+  static char ID;
+
+  RISCVMIPeepholeOpt() : MachineFunctionPass(ID) {
+    initializeRISCVMIPeepholeOptPass(*PassRegistry::getPassRegistry());
+  }
+
+  const RISCVInstrInfo *TII;
+
+  bool visitBranch(MachineInstr &MI);
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  StringRef getPassName() const override {
+    return "RISC-V MI Peephole Optimization pass";
+  }
+};
+
+char RISCVMIPeepholeOpt::ID = 0;
+
+} // end anonymous namespace
+
+INITIALIZE_PASS(RISCVMIPeepholeOpt, "riscv-mi-peephole-opt",
+                "RISC-V MI Peephole Optimization", false, false)
+
+bool RISCVMIPeepholeOpt::visitBranch(MachineInstr &MI) {
+  Register FirstReg = MI.getOperand(0).getReg();
+  Register SecondReg = MI.getOperand(1).getReg();
+
+  if (FirstReg != SecondReg)
+    return false;
+
+  switch (MI.getOpcode()) {
+  default:
+    break;
+  case RISCV::BEQ:
+  case RISCV::BGE:
+  case RISCV::BGEU:
+    BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(RISCV::JAL))
+        .addReg(RISCV::X0)
+        .add(MI.getOperand(2));
+    break;
+  }
+  MI.eraseFromParent();
+
+  return true;
+}
+
+bool RISCVMIPeepholeOpt::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(MF.getFunction()))
+    return false;
+
+  TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
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zengdage wrote:

I have changed it.

https://github.com/llvm/llvm-project/pull/90451