[llvm] [VP][RISCV] Add vp.cttz.elts intrinsic and its RISC-V codegen (PR #90502)

[Min-Yih Hsu via llvm-commits]

mshockwave wrote:

> > I wish I could test the expansion logics (i.e. fallback) for this intrinsics but `vfirst` is in every RVV extensions and AArch64 doesn't really support the combination of VP intrinsics + scalable vectors.
> 
> Can you test it with fixed vectors on another target?

I tried with something like
```
define i32 @fixed_v4i32(<4 x i32> %src, <4 x i1> %m, i32 %evl) {
   %r = call i32 @llvm.vp.cttz.elts.i32.v4i32(<4 x i32> %src, i1 0, <4 x i1> %m, i32 %evl)
   ret i32 %r
}
```
With AArch64 (both with and without SVE). And it failed during type legalization when it tried to promote EVL from i32 to i64. I'm not sure if I'm missing any flags

https://github.com/llvm/llvm-project/pull/90502