[llvm] [RISCV] Codegen support for XCVbi extension (PR #89719)

[Craig Topper via llvm-commits]

================
@@ -17678,7 +17682,8 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
       continue;
     if (isSelectPseudo(*SequenceMBBI)) {
       if (SequenceMBBI->getOperand(1).getReg() != LHS ||
-          SequenceMBBI->getOperand(2).getReg() != RHS ||
+          (SequenceMBBI->getOperand(2).isReg() &&
----------------
topperc wrote:

If its not a register this entire `if` needs to evaluate to false instead of just skipping the operand.

```
SequenceMBBI->getOperand(1).getReg() != LHS ||
!SequenceMBBI->getOperand(2).isReg() ||
SequenceMBBI->getOperand(2).getReg() != RHS || 
SequenceMBBI->getOperand(3).getImm() != CC ||
..
```

https://github.com/llvm/llvm-project/pull/89719