[llvm] [VP][RISCV] Add vp.cttz.elts intrinsic and its RISC-V codegen (PR #90502)

[Craig Topper via llvm-commits]

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@@ -6924,6 +6956,35 @@ SDValue DAGTypeLegalizer::WidenVecOp_VSELECT(SDNode *N) {
                      DAG.getVectorIdxConstant(0, DL));
 }
 
+SDValue DAGTypeLegalizer::WidenVecOp_VP_CttzElements(SDNode *N) {
+  // Widen the result bit width if needed.
+  SDLoc DL(N);
+  EVT OrigResVT = N->getValueType(0);
+  const Function &F = DAG.getMachineFunction().getFunction();
+
+  SDValue Source = GetWidenedVector(N->getOperand(0));
+  EVT SrcVT = Source.getValueType();
+  SDValue Mask =
+      GetWidenedMask(N->getOperand(1), SrcVT.getVectorElementCount());
+
+  // Compute the number of bits that can fit the result.
+  ConstantRange CR(APInt(64, SrcVT.getVectorMinNumElements()));
+  if (SrcVT.isScalableVT())
+    CR = CR.umul_sat(getVScaleRange(&F, 64));
+  // If the zero-is-poison flag is set in the original intrinsic, we can
+  // assume the upper limit of the result is EVL - 1.
+  if (N->getOpcode() == ISD::VP_CTTZ_ELTS_ZERO_UNDEF)
+    CR = CR.subtract(APInt(64, 1));
+
+  unsigned NewResWidth = OrigResVT.getScalarSizeInBits();
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topperc wrote:

Why do we need a new result width? The result should still be bound by the original EVL.

https://github.com/llvm/llvm-project/pull/90502