[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

================
@@ -1705,11 +1875,16 @@ void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
     MachineInstr &MI = *I++;
     if (RISCV::isFaultFirstLoad(MI)) {
       Register VLOutput = MI.getOperand(1).getReg();
-      if (!MRI->use_nodbg_empty(VLOutput))
-        BuildMI(MBB, I, MI.getDebugLoc(), TII->get(RISCV::PseudoReadVL),
-                VLOutput);
+      bool IsVirtual = MI.getOperand(1).getReg().isVirtual();
----------------
BeMg wrote:

>From `llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll`
```
;; llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh      -verify-machineinstrs
define <vscale x 16 x i16> @test_vlseg2ff_dead_vl(ptr %base, i64 %vl) {
entry:
  %0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, ptr %base, i64 %vl)
  %1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
  ret <vscale x 16 x i16> %1
}
```

During the `RISCVInsertVSETVLI::insertReadVL`, VLOutput will be `x0`

```
********** MACHINEINSTRS **********
# Machine code for function test_vlseg2ff_dead_vl: NoPHIs, TracksLiveness, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10 in %0, $x11 in %1
                                                                                                                                                                                                                                                                                        0B      bb.0.entry:
          liveins: $x10, $x11
16B       %1:gprnox0 = COPY $x11
32B       %0:gpr = COPY $x10
36B       dead $x0 = PseudoVSETVLI %1:gprnox0, 202, implicit-def $vl, implicit-def $vtype
48B       renamable $v4m4_v8m4, dead $x0 = PseudoVLSEG2E16FF_V_M4 undef renamable $v4m4_v8m4(tied-def 0), %0:gpr, $noreg, 4, 2, implicit-def dead $vl, implicit $vl, implicit $vtype :: (load unknown-size from %ir.base, align 2)
96B       PseudoRET implicit $v8m4
```

https://github.com/llvm/llvm-project/pull/70549