[llvm] [AMDGPU][AsmParser] Do not use predicates for validation of NamedIntOperands. (PR #90251)
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 29 02:49:34 PDT 2024
https://github.com/kosarev updated https://github.com/llvm/llvm-project/pull/90251
>From cb06d8dc316cf02ef042570aa4c6373b4d1e5e9b Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Fri, 26 Apr 2024 19:47:15 +0100
Subject: [PATCH] [AMDGPU][AsmParser] Do not use predicates for validation of
NamedIntOperands.
Their job is to discriminate between different types of operands,
not to check if they are valid. For validation we can use
conversion functions.
Clears the road to generating predicates automatically.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 28 +++++--------
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 40 ++++++++++++++-----
llvm/test/MC/AMDGPU/ds-err.s | 8 ++--
llvm/test/MC/AMDGPU/gfx11_asm_err.s | 4 +-
llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s | 2 +-
5 files changed, 45 insertions(+), 37 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index c4ec7a7befd47e..510f5bbf255527 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -385,8 +385,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isIdxen() const { return isImmTy(ImmTyIdxen); }
bool isAddr64() const { return isImmTy(ImmTyAddr64); }
bool isOffset() const { return isImmTy(ImmTyOffset); }
- bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }
- bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }
+ bool isOffset0() const { return isImmTy(ImmTyOffset0); }
+ bool isOffset1() const { return isImmTy(ImmTyOffset1); }
bool isSMEMOffsetMod() const { return isImmTy(ImmTySMEMOffsetMod); }
bool isFlatOffset() const { return isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset); }
bool isGDS() const { return isImmTy(ImmTyGDS); }
@@ -411,9 +411,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
bool isNegLo() const { return isImmTy(ImmTyNegLo); }
bool isNegHi() const { return isImmTy(ImmTyNegHi); }
- bool isByteSel() const {
- return isImmTy(ImmTyByteSel) && isUInt<2>(getImm());
- }
+ bool isByteSel() const { return isImmTy(ImmTyByteSel); }
bool isRegOrImm() const {
return isReg() || isImm();
@@ -8939,11 +8937,11 @@ bool AMDGPUOperand::isBLGP() const {
}
bool AMDGPUOperand::isCBSZ() const {
- return isImm() && getImmTy() == ImmTyCBSZ && isUInt<3>(getImm());
+ return isImm() && getImmTy() == ImmTyCBSZ;
}
bool AMDGPUOperand::isABID() const {
- return isImm() && getImmTy() == ImmTyABID && isUInt<4>(getImm());
+ return isImm() && getImmTy() == ImmTyABID;
}
bool AMDGPUOperand::isS16Imm() const {
@@ -9670,25 +9668,17 @@ bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }
// LDSDIR
//===----------------------------------------------------------------------===//
-bool AMDGPUOperand::isWaitVDST() const {
- return isImmTy(ImmTyWaitVDST) && isUInt<4>(getImm());
-}
+bool AMDGPUOperand::isWaitVDST() const { return isImmTy(ImmTyWaitVDST); }
-bool AMDGPUOperand::isWaitVAVDst() const {
- return isImmTy(ImmTyWaitVAVDst) && isUInt<4>(getImm());
-}
+bool AMDGPUOperand::isWaitVAVDst() const { return isImmTy(ImmTyWaitVAVDst); }
-bool AMDGPUOperand::isWaitVMVSrc() const {
- return isImmTy(ImmTyWaitVMVSrc) && isUInt<1>(getImm());
-}
+bool AMDGPUOperand::isWaitVMVSrc() const { return isImmTy(ImmTyWaitVMVSrc); }
//===----------------------------------------------------------------------===//
// VINTERP
//===----------------------------------------------------------------------===//
-bool AMDGPUOperand::isWaitEXP() const {
- return isImmTy(ImmTyWaitEXP) && isUInt<3>(getImm());
-}
+bool AMDGPUOperand::isWaitEXP() const { return isImmTy(ImmTyWaitEXP); }
//===----------------------------------------------------------------------===//
// Split Barrier
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index bf6cfe90ebfbee..7189e6e4050631 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1000,8 +1000,10 @@ def SDWAVopcDst : BoolRC {
}
class NamedIntOperand<ValueType Type, string Prefix, bit Optional = 1,
- string name = NAME, string ConvertMethod = "nullptr">
+ string name = NAME>
: CustomOperand<Type, Optional, name> {
+ string Validator = "[](int64_t V) { return true; }";
+ string ConvertMethod = "[](int64_t &V) { return "#Validator#"(V); }";
let ParserMethod =
"[this](OperandVector &Operands) -> ParseStatus { "#
"return parseIntWithPrefix(\""#Prefix#"\", Operands, "#
@@ -1045,8 +1047,10 @@ class ArrayOperand0<string Id, string Name = NAME>
let ImmTy = "ImmTyOffset" in
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
def Offset : NamedIntOperand<i32, "offset">;
+let Validator = "isUInt<8>" in {
def Offset0 : NamedIntOperand<i8, "offset0">;
def Offset1 : NamedIntOperand<i8, "offset1">;
+}
def gds : NamedBitOperand<"gds", "GDS">;
@@ -1103,27 +1107,41 @@ let DefaultValue = "0xf" in {
def DppRowMask : NamedIntOperand<i32, "row_mask">;
def DppBankMask : NamedIntOperand<i32, "bank_mask">;
}
-def DppBoundCtrl : NamedIntOperand<i1, "bound_ctrl", 1, "DppBoundCtrl",
- "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }">;
+def DppBoundCtrl : NamedIntOperand<i1, "bound_ctrl"> {
+ let ConvertMethod = "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }";
+}
let DecoderMethod = "decodeDpp8FI" in
def Dpp8FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
def Dpp16FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
def blgp : CustomOperand<i32, 1, "BLGP">;
-def CBSZ : NamedIntOperand<i32, "cbsz">;
-def ABID : NamedIntOperand<i32, "abid">;
-
+def CBSZ : NamedIntOperand<i32, "cbsz"> {
+ let Validator = "isUInt<3>";
+}
+def ABID : NamedIntOperand<i32, "abid"> {
+ let Validator = "isUInt<4>";
+}
def hwreg : CustomOperand<i32, 0, "Hwreg">;
def exp_tgt : CustomOperand<i32, 0, "ExpTgt">;
-def WaitVDST : NamedIntOperand<i8, "wait_vdst">;
-def WaitEXP : NamedIntOperand<i8, "wait_exp">;
-def WaitVAVDst : NamedIntOperand<i8, "wait_va_vdst">;
-def WaitVMVSrc : NamedIntOperand<i8, "wait_vm_vsrc">;
+def WaitVDST : NamedIntOperand<i8, "wait_vdst"> {
+ let Validator = "isUInt<4>";
+}
+def WaitEXP : NamedIntOperand<i8, "wait_exp"> {
+ let Validator = "isUInt<3>";
+}
+def WaitVAVDst : NamedIntOperand<i8, "wait_va_vdst"> {
+ let Validator = "isUInt<4>";
+}
+def WaitVMVSrc : NamedIntOperand<i8, "wait_vm_vsrc"> {
+ let Validator = "isUInt<1>";
+}
-def ByteSel : NamedIntOperand<i8, "byte_sel">;
+def ByteSel : NamedIntOperand<i8, "byte_sel"> {
+ let Validator = "isUInt<2>";
+}
class KImmFPOperand<ValueType vt> : ImmOperand<vt> {
let OperandNamespace = "AMDGPU";
diff --git a/llvm/test/MC/AMDGPU/ds-err.s b/llvm/test/MC/AMDGPU/ds-err.s
index 2d25fdf5e302d1..c31f4c7593950e 100644
--- a/llvm/test/MC/AMDGPU/ds-err.s
+++ b/llvm/test/MC/AMDGPU/ds-err.s
@@ -18,19 +18,19 @@ ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
ds_write2_b32 v2, v4, v6 offset1:4 offset1:8
// offset0 too big
-// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset0 value.
ds_write2_b32 v2, v4, v6 offset0:1000000000
// offset0 too big
-// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset0 value.
ds_write2_b32 v2, v4, v6 offset0:0x100
// offset1 too big
-// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset1 value.
ds_write2_b32 v2, v4, v6 offset1:1000000000
// offset1 too big
-// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset1 value.
ds_write2_b32 v2, v4, v6 offset1:0x100
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_err.s
index 3ec31626be5b70..7f99afe0192599 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_err.s
@@ -22,13 +22,13 @@ s_delay_alu instid0(VALU_DEP_1) | SALU_CYCLE_1)
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left parenthesis
lds_direct_load v15 wait_vdst:16
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid wait_vdst value.
lds_direct_load v15 wait_vdst
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
v_interp_p10_f32 v0, v1, v2, v3 wait_exp:8
-// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid wait_exp value.
v_interp_p2_f32 v0, -v1, v2, v3 wait_exp
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
index 31ed577ac0a233..a9dd290ea67d87 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
@@ -103,6 +103,6 @@ v_permlane16_var_b32 v5, v1, v2 op_sel:[0, 0, 1]
// GFX12-NEXT:{{^}} ^
v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:4
-// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid byte_sel value.
// GFX12-NEXT:{{^}}v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:4
// GFX12-NEXT:{{^}} ^
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