[llvm] [SelectionDAG]: Have isKnownNeverZero treat SRL like division if all else fails (PR #89523)
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Sun Apr 21 05:55:25 PDT 2024
https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/89523
>From 1611a27df6b2f73328c88235cb532ae75153bd19 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Sat, 20 Apr 2024 21:31:50 -0400
Subject: [PATCH 1/2] [SelectionDAG]: Have isKnownNeverZero treat SRL like
division if all else fails
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 7dbf83b7adeef0..0ac493ba5e6c33 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5443,10 +5443,19 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
if (ValKnown.isNegative())
return true;
// If max shift cnt of known ones is non-zero, result is non-zero.
- APInt MaxCnt = computeKnownBits(Op.getOperand(1), Depth + 1).getMaxValue();
+ const KnownBits Shift = computeKnownBits(Op.getOperand(1), Depth + 1);
+ APInt MaxCnt = Shift.getMaxValue();
if (MaxCnt.ult(ValKnown.getBitWidth()) &&
!ValKnown.One.lshr(MaxCnt).isZero())
return true;
+ // We try to see if we can turn it into a division
+ const KnownBits One =
+ KnownBits::makeConstant(APInt(ValKnown.getBitWidth(), 1));
+
+ std::optional<bool> uge =
+ KnownBits::uge(ValKnown, KnownBits::shl(One, Shift));
+ if (uge && *uge)
+ return true;
break;
}
case ISD::UDIV:
>From 24b64bade70e73e4f36a2d682eb5fc258adb3455 Mon Sep 17 00:00:00 2001
From: AtariDreams <gfunni234 at gmail.com>
Date: Sun, 21 Apr 2024 08:55:16 -0400
Subject: [PATCH 2/2] Make requested changes
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 0ac493ba5e6c33..6dc7f79b84be08 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5445,8 +5445,9 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
// If max shift cnt of known ones is non-zero, result is non-zero.
const KnownBits Shift = computeKnownBits(Op.getOperand(1), Depth + 1);
APInt MaxCnt = Shift.getMaxValue();
- if (MaxCnt.ult(ValKnown.getBitWidth()) &&
- !ValKnown.One.lshr(MaxCnt).isZero())
+ if (MaxCnt.uge(ValKnown.getBitWidth())
+ return false;
+ if (!ValKnown.One.lshr(MaxCnt).isZero())
return true;
// We try to see if we can turn it into a division
const KnownBits One =
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