[llvm] [SelectionDAG]: Add more cases for UDIV, SDIV, SRA, and SRL (PR #89522)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff 811ffc049ff914e15116c25ca8db7b8bd9a8e186 6d77b80722eb41a9d635367aeee6df6103398bf5 -- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/lib/Support/KnownBits.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 39403b1f98..be9af7b58b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5451,8 +5451,9 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
     // Similar to udiv but we try to see if we can turn it into a division
     const KnownBits One =
         KnownBits::makeConstant(APInt(ValKnown.getBitWidth(), 1));
-    
-    std::optional<bool> uge = KnownBits::uge(ValKnown, KnownBits::shl(One, Shift));
+
+    std::optional<bool> uge =
+        KnownBits::uge(ValKnown, KnownBits::shl(One, Shift));
     if (uge && *uge)
       return true;
     break;
@@ -5483,8 +5484,8 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
 
     // For negative numbers, the comparison is reversed. Op0 <= Op1
     if (Op0.isNegative() && Op1.isNegative()) {
-       std::optional<bool> sle =  KnownBits::sle(Op0, Op1);
-       if (sle && *sle)
+      std::optional<bool> sle = KnownBits::sle(Op0, Op1);
+      if (sle && *sle)
         return true;
     }
 

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https://github.com/llvm/llvm-project/pull/89522