[llvm] [SelectionDAG]: Have isKnownNeverZero treat SRL like division if all else fails (PR #89523)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff 6cebd3577245a687947506ff423ea726ccd80849 9d5f80f5a2a7537f31d6be9c3e6956ef41ea52d1 -- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index b32cb8ab05..0ac493ba5e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5451,8 +5451,9 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
     // We try to see if we can turn it into a division
     const KnownBits One =
         KnownBits::makeConstant(APInt(ValKnown.getBitWidth(), 1));
-    
-    std::optional<bool> uge = KnownBits::uge(ValKnown, KnownBits::shl(One, Shift));
+
+    std::optional<bool> uge =
+        KnownBits::uge(ValKnown, KnownBits::shl(One, Shift));
     if (uge && *uge)
       return true;
     break;

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https://github.com/llvm/llvm-project/pull/89523