[llvm] 6cebd35 - [RISCV] Remove extra indentation from RISCVProcessors.td.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-04-20T19:21:59-07:00
New Revision: 6cebd3577245a687947506ff423ea726ccd80849

URL: https://github.com/llvm/llvm-project/commit/6cebd3577245a687947506ff423ea726ccd80849
DIFF: https://github.com/llvm/llvm-project/commit/6cebd3577245a687947506ff423ea726ccd80849.diff

LOG: [RISCV] Remove extra indentation from RISCVProcessors.td.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVProcessors.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 3c86036e65fa28..a4a5d9e96c271a 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -44,7 +44,7 @@ class RISCVProcessorModel<string n,
                           list<SubtargetFeature> f,
                           list<SubtargetFeature> tunef = [],
                           string default_march = "">
-      :  ProcessorModel<n, m, f, tunef> {
+    :  ProcessorModel<n, m, f, tunef> {
   string DefaultMarch = default_march;
 }
 
@@ -52,7 +52,7 @@ class RISCVTuneProcessorModel<string n,
                               SchedMachineModel m,
                               list<SubtargetFeature> tunef = [],
                               list<SubtargetFeature> f = []>
-      : ProcessorModel<n, m, f,tunef>;
+    : ProcessorModel<n, m, f,tunef>;
 
 def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
                                        NoSchedModel,