[llvm] [RISCV] Add extension information to RISCVFeatures.td. NFC (PR #89326)
Brandon Wu via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 20 02:36:42 PDT 2024
================
@@ -500,136 +536,138 @@ def HasStdExtZkndOrZkne
"'Zkne' (NIST Suite: AES Encryption)">;
def FeatureStdExtZknh
- : SubtargetFeature<"zknh", "HasStdExtZknh", "true",
- "'Zknh' (NIST Suite: Hash Function Instructions)">;
+ : RISCVExtension<"zknh", 1, 0, "HasStdExtZknh",
+ "'Zknh' (NIST Suite: Hash Function Instructions)">;
def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
AssemblerPredicate<(all_of FeatureStdExtZknh),
"'Zknh' (NIST Suite: Hash Function Instructions)">;
def FeatureStdExtZksed
- : SubtargetFeature<"zksed", "HasStdExtZksed", "true",
- "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
+ : RISCVExtension<"zksed", 1, 0, "HasStdExtZksed",
+ "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
AssemblerPredicate<(all_of FeatureStdExtZksed),
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
def FeatureStdExtZksh
- : SubtargetFeature<"zksh", "HasStdExtZksh", "true",
- "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
+ : RISCVExtension<"zksh", 1, 0, "HasStdExtZksh",
+ "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
AssemblerPredicate<(all_of FeatureStdExtZksh),
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
def FeatureStdExtZkr
- : SubtargetFeature<"zkr", "HasStdExtZkr", "true",
- "'Zkr' (Entropy Source Extension)">;
+ : RISCVExtension<"zkr", 1, 0, "HasStdExtZkr",
+ "'Zkr' (Entropy Source Extension)">;
def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
AssemblerPredicate<(all_of FeatureStdExtZkr),
"'Zkr' (Entropy Source Extension)">;
def FeatureStdExtZkn
- : SubtargetFeature<"zkn", "HasStdExtZkn", "true",
- "'Zkn' (NIST Algorithm Suite)",
- [FeatureStdExtZbkb,
- FeatureStdExtZbkc,
- FeatureStdExtZbkx,
- FeatureStdExtZkne,
- FeatureStdExtZknd,
- FeatureStdExtZknh]>;
+ : RISCVExtension<"zkn", 1, 0, "HasStdExtZkn",
+ "'Zkn' (NIST Algorithm Suite)",
+ [FeatureStdExtZbkb,
+ FeatureStdExtZbkc,
+ FeatureStdExtZbkx,
+ FeatureStdExtZkne,
+ FeatureStdExtZknd,
+ FeatureStdExtZknh]>;
def FeatureStdExtZks
- : SubtargetFeature<"zks", "HasStdExtZks", "true",
- "'Zks' (ShangMi Algorithm Suite)",
- [FeatureStdExtZbkb,
- FeatureStdExtZbkc,
- FeatureStdExtZbkx,
- FeatureStdExtZksed,
- FeatureStdExtZksh]>;
+ : RISCVExtension<"zks", 1, 0, "HasStdExtZks",
+ "'Zks' (ShangMi Algorithm Suite)",
+ [FeatureStdExtZbkb,
+ FeatureStdExtZbkc,
+ FeatureStdExtZbkx,
+ FeatureStdExtZksed,
+ FeatureStdExtZksh]>;
def FeatureStdExtZkt
- : SubtargetFeature<"zkt", "HasStdExtZkt", "true",
- "'Zkt' (Data Independent Execution Latency)">;
+ : RISCVExtension<"zkt", 1, 0, "HasStdExtZkt",
+ "'Zkt' (Data Independent Execution Latency)">;
def FeatureStdExtZk
- : SubtargetFeature<"zk", "HasStdExtZk", "true",
- "'Zk' (Standard scalar cryptography extension)",
- [FeatureStdExtZkn,
- FeatureStdExtZkr,
- FeatureStdExtZkt]>;
+ : RISCVExtension<"zk", 1, 0, "HasStdExtZk",
+ "'Zk' (Standard scalar cryptography extension)",
+ [FeatureStdExtZkn,
+ FeatureStdExtZkr,
+ FeatureStdExtZkt]>;
// Vector Extensions
-def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",
- "'Zvl' (Minimum Vector Length) 32">;
+def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0, "ZvlLen",
+ "'Zvl' (Minimum Vector Length) 32", [],
+ "32">;
foreach i = { 6-16 } in {
defvar I = !shl(1, i);
def FeatureStdExtZvl#I#b :
- SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I),
- "'Zvl' (Minimum Vector Length) "#I,
- [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
+ RISCVExtension<"zvl"#I#"b", 1, 0, "ZvlLen",
+ "'Zvl' (Minimum Vector Length) "#I,
+ [!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],
+ !cast<string>(I)>;
}
def FeatureStdExtZve32x
- : SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
- "'Zve32x' (Vector Extensions for Embedded Processors "
- "with maximal 32 EEW)",
- [FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
+ : RISCVExtension<"zve32x", 1, 0, "HasStdExtZve32x",
+ "'Zve32x' (Vector Extensions for Embedded Processors "
----------------
4vtomat wrote:
Wrong indentation.
https://github.com/llvm/llvm-project/pull/89326
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