[llvm] [RISCV][TableGen] Generate RISCVTargetParser.inc from the new RISCVExtension tblgen information. (PR #89335)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 19 16:41:22 PDT 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/89335
>From b379f21070e8409da463e7df14006cbd9131ddaa Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 15 Apr 2024 12:31:36 -0700
Subject: [PATCH 1/7] [RISCV] Add extension information to RISCVFeatures.td.
NFC
This adds a new RISCVExtension class that inherits from SubtargetFeature.
This contains the major/minor version and whether the extension is
experimental. The plan is to use this to generate the tables for
RISCVISAInfo.cpp.
The version numbers might not be accurate yet. If there are errors
they will be fixed before they are used for anything. It will be easier
to verify once the new tablegen backend is written to generate the
RISCVISAInfo.cpp table.
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 777 +++++++++++++------------
1 file changed, 395 insertions(+), 382 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 339c0397fa4518..b9034e7236b41b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -10,115 +10,129 @@
// RISC-V subtarget features and instruction predicates.
//===----------------------------------------------------------------------===//
+class RISCVExtension<string n, int major, int minor, string f, string v,
+ string d, list<RISCVExtension> i = []>
+ : SubtargetFeature<n, f, v, d,
+ !foreach(feature, i, !cast<SubtargetFeature>(feature))> {
+ int MajorVersion = major;
+ int MinorVersion = minor;
+ bit Experimental = false;
+}
+
+class RISCVExperimentalExtension<string n, int major, int minor, string f,
+ string v, string d, list<RISCVExtension> i = []>
+ : RISCVExtension<"experimental-"#n, major, minor, f, v, d, i> {
+ let Experimental = true;
+}
+
// Integer Extensions
def FeatureStdExtI
- : SubtargetFeature<"i", "HasStdExtI", "true",
- "'I' (Base Integer Instruction Set)">;
-
+ : RISCVExtension<"i", 2, 1, "HasStdExtI", "true",
+ "'I' (Base Integer Instruction Set)">;
def FeatureStdExtZic64b
- : SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
- "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+ : RISCVExtension<"zic64b", 1, 0, "HasStdExtZic64b", "true",
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
def FeatureStdExtZicbom
- : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
- "'Zicbom' (Cache-Block Management Instructions)">;
+ : RISCVExtension<"zicbom", 1, 0, "HasStdExtZicbom", "true",
+ "'Zicbom' (Cache-Block Management Instructions)">;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
def FeatureStdExtZicbop
- : SubtargetFeature<"zicbop", "HasStdExtZicbop", "true",
- "'Zicbop' (Cache-Block Prefetch Instructions)">;
+ : RISCVExtension<"zicbop", 1, 0, "HasStdExtZicbop", "true",
+ "'Zicbop' (Cache-Block Prefetch Instructions)">;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
def FeatureStdExtZicboz
- : SubtargetFeature<"zicboz", "HasStdExtZicboz", "true",
- "'Zicboz' (Cache-Block Zero Instructions)">;
+ : RISCVExtension<"zicboz", 1, 0, "HasStdExtZicboz", "true",
+ "'Zicboz' (Cache-Block Zero Instructions)">;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
def FeatureStdExtZiccamoa
- : SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
- "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+ : RISCVExtension<"ziccamoa", 1, 0, "HasStdExtZiccamoa", "true",
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
def FeatureStdExtZiccif
- : SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
- "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
+ : RISCVExtension<"ziccif", 1, 0, "HasStdExtZiccif", "true",
+ "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
def FeatureStdExtZicclsm
- : SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
- "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
+ : RISCVExtension<"zicclsm", 1, 0, "HasStdExtZicclsm", "true",
+ "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
def FeatureStdExtZiccrse
- : SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
- "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
+ : RISCVExtension<"ziccrse", 1, 0, "HasStdExtZiccrse", "true",
+ "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
def FeatureStdExtZicsr
- : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
- "'zicsr' (CSRs)">;
+ : RISCVExtension<"zicsr", 2, 0, "HasStdExtZicsr", "true",
+ "'zicsr' (CSRs)">;
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
def FeatureStdExtZicntr
- : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
- "'Zicntr' (Base Counters and Timers)",
+ : RISCVExtension<"zicntr", 2, 0, "HasStdExtZicntr", "true",
+ "'Zicntr' (Base Counters and Timers)",
[FeatureStdExtZicsr]>;
def FeatureStdExtZicond
- : SubtargetFeature<"zicond", "HasStdExtZicond", "true",
- "'Zicond' (Integer Conditional Operations)">;
+ : RISCVExtension<"zicond", 1, 0, "HasStdExtZicond", "true",
+ "'Zicond' (Integer Conditional Operations)">;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
def FeatureStdExtZifencei
- : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
- "'Zifencei' (fence.i)">;
+ : RISCVExtension<"zifencei", 2, 0, "HasStdExtZifencei", "true",
+ "'Zifencei' (fence.i)">;
def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
def FeatureStdExtZihintpause
- : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
- "'Zihintpause' (Pause Hint)">;
+ : RISCVExtension<"zihintpause", 2, 0, "HasStdExtZihintpause", "true",
+ "'Zihintpause' (Pause Hint)">;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
def FeatureStdExtZihintntl
- : SubtargetFeature<"zihintntl", "HasStdExtZihintntl", "true",
+ : RISCVExtension<"zihintntl", 1, 0, "HasStdExtZihintntl", "true",
"'Zihintntl' (Non-Temporal Locality Hints)">;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
def FeatureStdExtZihpm
- : SubtargetFeature<"zihpm", "HasStdExtZihpm", "true",
- "'Zihpm' (Hardware Performance Counters)",
- [FeatureStdExtZicsr]>;
+ : RISCVExtension<"zihpm", 2, 0, "HasStdExtZihpm", "true",
+ "'Zihpm' (Hardware Performance Counters)",
+ [FeatureStdExtZicsr]>;
-def FeatureStdExtZimop : SubtargetFeature<"zimop", "HasStdExtZimop", "true",
- "'Zimop' (May-Be-Operations)">;
+def FeatureStdExtZimop : RISCVExtension<"zimop", 1, 0, "HasStdExtZimop", "true",
+ "'Zimop' (May-Be-Operations)">;
def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
def FeatureStdExtZicfilp
- : SubtargetFeature<"experimental-zicfilp", "HasStdExtZicfilp", "true",
- "'Zicfilp' (Landing pad)">;
+ : RISCVExperimentalExtension<"zicfilp", 0, 4, "HasStdExtZicfilp", "true",
+ "'Zicfilp' (Landing pad)">;
def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
AssemblerPredicate<(all_of FeatureStdExtZicfilp),
"'Zicfilp' (Landing pad)">;
def FeatureStdExtZicfiss
- : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true",
- "'Zicfiss' (Shadow stack)",
- [FeatureStdExtZicsr, FeatureStdExtZimop]>;
+ : RISCVExperimentalExtension<"zicfiss", 0, 4, "HasStdExtZicfiss", "true",
+ "'Zicfiss' (Shadow stack)",
+ [FeatureStdExtZicsr, FeatureStdExtZimop]>;
def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
AssemblerPredicate<(all_of FeatureStdExtZicfiss),
"'Zicfiss' (Shadow stack)">;
@@ -127,15 +141,15 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
// Multiply Extensions
def FeatureStdExtM
- : SubtargetFeature<"m", "HasStdExtM", "true",
- "'M' (Integer Multiplication and Division)">;
+ : RISCVExtension<"m", 2, 0, "HasStdExtM", "true",
+ "'M' (Integer Multiplication and Division)">;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
def FeatureStdExtZmmul
- : SubtargetFeature<"zmmul", "HasStdExtZmmul", "true",
- "'Zmmul' (Integer Multiplication)">;
+ : RISCVExtension<"zmmul", 1, 0, "HasStdExtZmmul", "true",
+ "'Zmmul' (Integer Multiplication)">;
def HasStdExtMOrZmmul
: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
@@ -146,28 +160,28 @@ def HasStdExtMOrZmmul
// Atomic Extensions
def FeatureStdExtA
- : SubtargetFeature<"a", "HasStdExtA", "true",
- "'A' (Atomic Instructions)">;
+ : RISCVExtension<"a", 2, 1, "HasStdExtA", "true",
+ "'A' (Atomic Instructions)">;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
def FeatureStdExtZtso
- : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
- "'Ztso' (Memory Model - Total Store Order)">;
+ : RISCVExperimentalExtension<"ztso", 0, 1, "HasStdExtZtso", "true",
+ "'Ztso' (Memory Model - Total Store Order)">;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
-def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true",
- "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
+def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0, "HasStdExtZa64rs", "true",
+ "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
-def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true",
- "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
+def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0, "HasStdExtZa128rs", "true",
+ "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
def FeatureStdExtZaamo
- : SubtargetFeature<"experimental-zaamo", "HasStdExtZaamo", "true",
+ : RISCVExperimentalExtension<"zaamo", 0, 2, "HasStdExtZaamo", "true",
"'Zaamo' (Atomic Memory Operations)">;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
@@ -176,30 +190,30 @@ def HasStdExtAOrZaamo
"'Zaamo' (Atomic Memory Operations)">;
def FeatureStdExtZabha
- : SubtargetFeature<"experimental-zabha", "HasStdExtZabha", "true",
- "'Zabha' (Byte and Halfword Atomic Memory Operations)">;
+ : RISCVExperimentalExtension<"zabha", 1, 0, "HasStdExtZabha", "true",
+ "'Zabha' (Byte and Halfword Atomic Memory Operations)">;
def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
AssemblerPredicate<(all_of FeatureStdExtZabha),
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
def FeatureStdExtZacas
- : SubtargetFeature<"zacas", "HasStdExtZacas", "true",
- "'Zacas' (Atomic Compare-And-Swap Instructions)">;
+ : RISCVExtension<"zacas", 1, 0, "HasStdExtZacas", "true",
+ "'Zacas' (Atomic Compare-And-Swap Instructions)">;
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
AssemblerPredicate<(all_of FeatureStdExtZacas),
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
def FeatureStdExtZalasr
- : SubtargetFeature<"experimental-zalasr", "HasStdExtZalasr", "true",
- "'Zalasr' (Load-Acquire and Store-Release Instructions)">;
+ : RISCVExperimentalExtension<"zalasr", 0, 1, "HasStdExtZalasr", "true",
+ "'Zalasr' (Load-Acquire and Store-Release Instructions)">;
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
AssemblerPredicate<(all_of FeatureStdExtZalasr),
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
def FeatureStdExtZalrsc
- : SubtargetFeature<"experimental-zalrsc", "HasStdExtZalrsc", "true",
- "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+ : RISCVExperimentalExtension<"zalrsc", 0, 2, "HasStdExtZalrsc", "true",
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
@@ -207,11 +221,11 @@ def HasStdExtAOrZalrsc
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
def FeatureStdExtZama16b
- : SubtargetFeature<"zama16b", "HasStdExtZama16b", "true",
- "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
+ : RISCVExtension<"zama16b", 1, 0, "HasStdExtZama16b", "true",
+ "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
-def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
- "'Zawrs' (Wait on Reservation Set)">;
+def FeatureStdExtZawrs : RISCVExtension<"zawrs", 1, 0, "HasStdExtZawrs", "true",
+ "'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
AssemblerPredicate<(all_of FeatureStdExtZawrs),
"'Zawrs' (Wait on Reservation Set)">;
@@ -219,43 +233,43 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
// Floating Point Extensions
def FeatureStdExtF
- : SubtargetFeature<"f", "HasStdExtF", "true",
- "'F' (Single-Precision Floating-Point)",
- [FeatureStdExtZicsr]>;
+ : RISCVExtension<"f", 2, 2, "HasStdExtF", "true",
+ "'F' (Single-Precision Floating-Point)",
+ [FeatureStdExtZicsr]>;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
AssemblerPredicate<(all_of FeatureStdExtF),
"'F' (Single-Precision Floating-Point)">;
def FeatureStdExtD
- : SubtargetFeature<"d", "HasStdExtD", "true",
- "'D' (Double-Precision Floating-Point)",
- [FeatureStdExtF]>;
+ : RISCVExtension<"d", 2, 2, "HasStdExtD", "true",
+ "'D' (Double-Precision Floating-Point)",
+ [FeatureStdExtF]>;
def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<(all_of FeatureStdExtD),
"'D' (Double-Precision Floating-Point)">;
def FeatureStdExtZfhmin
- : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
- "'Zfhmin' (Half-Precision Floating-Point Minimal)",
- [FeatureStdExtF]>;
+ : RISCVExtension<"zfhmin", 1, 0, "HasStdExtZfhmin", "true",
+ "'Zfhmin' (Half-Precision Floating-Point Minimal)",
+ [FeatureStdExtF]>;
def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
"'Zfh' (Half-Precision Floating-Point) or "
"'Zfhmin' (Half-Precision Floating-Point Minimal)">;
def FeatureStdExtZfh
- : SubtargetFeature<"zfh", "HasStdExtZfh", "true",
- "'Zfh' (Half-Precision Floating-Point)",
- [FeatureStdExtZfhmin]>;
+ : RISCVExtension<"zfh", 1, 0, "HasStdExtZfh", "true",
+ "'Zfh' (Half-Precision Floating-Point)",
+ [FeatureStdExtZfhmin]>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
def FeatureStdExtZfbfmin
- : SubtargetFeature<"experimental-zfbfmin", "HasStdExtZfbfmin", "true",
- "'Zfbfmin' (Scalar BF16 Converts)",
- [FeatureStdExtF]>;
+ : RISCVExperimentalExtension<"zfbfmin", 1, 0, "HasStdExtZfbfmin", "true",
+ "'Zfbfmin' (Scalar BF16 Converts)",
+ [FeatureStdExtF]>;
def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
"'Zfbfmin' (Scalar BF16 Converts)">;
@@ -269,42 +283,42 @@ def HasHalfFPLoadStoreMove
"'Zfbfmin' (Scalar BF16 Converts)">;
def FeatureStdExtZfa
- : SubtargetFeature<"zfa", "HasStdExtZfa", "true",
- "'Zfa' (Additional Floating-Point)",
- [FeatureStdExtF]>;
+ : RISCVExtension<"zfa", 1, 0, "HasStdExtZfa", "true",
+ "'Zfa' (Additional Floating-Point)",
+ [FeatureStdExtF]>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
AssemblerPredicate<(all_of FeatureStdExtZfa),
"'Zfa' (Additional Floating-Point)">;
def FeatureStdExtZfinx
- : SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
- "'Zfinx' (Float in Integer)",
- [FeatureStdExtZicsr]>;
+ : RISCVExtension<"zfinx", 1, 0, "HasStdExtZfinx", "true",
+ "'Zfinx' (Float in Integer)",
+ [FeatureStdExtZicsr]>;
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
def FeatureStdExtZdinx
- : SubtargetFeature<"zdinx", "HasStdExtZdinx", "true",
- "'Zdinx' (Double in Integer)",
- [FeatureStdExtZfinx]>;
+ : RISCVExtension<"zdinx", 1, 0, "HasStdExtZdinx", "true",
+ "'Zdinx' (Double in Integer)",
+ [FeatureStdExtZfinx]>;
def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
AssemblerPredicate<(all_of FeatureStdExtZdinx),
"'Zdinx' (Double in Integer)">;
def FeatureStdExtZhinxmin
- : SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true",
- "'Zhinxmin' (Half Float in Integer Minimal)",
- [FeatureStdExtZfinx]>;
+ : RISCVExtension<"zhinxmin", 1, 0, "HasStdExtZhinxmin", "true",
+ "'Zhinxmin' (Half Float in Integer Minimal)",
+ [FeatureStdExtZfinx]>;
def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
"'Zhinx' (Half Float in Integer) or "
"'Zhinxmin' (Half Float in Integer Minimal)">;
def FeatureStdExtZhinx
- : SubtargetFeature<"zhinx", "HasStdExtZhinx", "true",
- "'Zhinx' (Half Float in Integer)",
- [FeatureStdExtZhinxmin]>;
+ : RISCVExtension<"zhinx", 1, 0, "HasStdExtZhinx", "true",
+ "'Zhinx' (Half Float in Integer)",
+ [FeatureStdExtZhinxmin]>;
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
AssemblerPredicate<(all_of FeatureStdExtZhinx),
"'Zhinx' (Half Float in Integer)">;
@@ -313,8 +327,8 @@ def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
// Compressed Extensions
def FeatureStdExtC
- : SubtargetFeature<"c", "HasStdExtC", "true",
- "'C' (Compressed Instructions)">;
+ : RISCVExtension<"c", 2, 0, "HasStdExtC", "true",
+ "'C' (Compressed Instructions)">;
def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
"'C' (Compressed Instructions)">;
@@ -327,9 +341,9 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
"RVC Hint Instructions">;
def FeatureStdExtZca
- : SubtargetFeature<"zca", "HasStdExtZca", "true",
- "'Zca' (part of the C extension, excluding compressed "
- "floating point loads/stores)">;
+ : RISCVExtension<"zca", 1, 0, "HasStdExtZca", "true",
+ "'Zca' (part of the C extension, excluding compressed "
+ "floating point loads/stores)">;
def HasStdExtCOrZca
: Predicate<"Subtarget->hasStdExtCOrZca()">,
@@ -339,49 +353,49 @@ def HasStdExtCOrZca
"compressed floating point loads/stores)">;
def FeatureStdExtZcb
- : SubtargetFeature<"zcb", "HasStdExtZcb", "true",
- "'Zcb' (Compressed basic bit manipulation instructions)",
- [FeatureStdExtZca]>;
+ : RISCVExtension<"zcb", 1, 0, "HasStdExtZcb", "true",
+ "'Zcb' (Compressed basic bit manipulation instructions)",
+ [FeatureStdExtZca]>;
def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
AssemblerPredicate<(all_of FeatureStdExtZcb),
"'Zcb' (Compressed basic bit manipulation instructions)">;
def FeatureStdExtZcd
- : SubtargetFeature<"zcd", "HasStdExtZcd", "true",
- "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
- [FeatureStdExtZca]>;
+ : RISCVExtension<"zcd", 1, 0, "HasStdExtZcd", "true",
+ "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
+ [FeatureStdExtZca]>;
def HasStdExtCOrZcd
: Predicate<"Subtarget->hasStdExtCOrZcd()">,
AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
- "'C' (Compressed Instructions) or "
- "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
+ "'C' (Compressed Instructions) or "
+ "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
def FeatureStdExtZcf
- : SubtargetFeature<"zcf", "HasStdExtZcf", "true",
- "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
- [FeatureStdExtZca]>;
+ : RISCVExtension<"zcf", 1, 0, "HasStdExtZcf", "true",
+ "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
+ [FeatureStdExtZca]>;
def FeatureStdExtZcmp
- : SubtargetFeature<"zcmp", "HasStdExtZcmp", "true",
- "'Zcmp' (sequenced instuctions for code-size reduction)",
- [FeatureStdExtZca]>;
+ : RISCVExtension<"zcmp", 1, 0, "HasStdExtZcmp", "true",
+ "'Zcmp' (sequenced instuctions for code-size reduction)",
+ [FeatureStdExtZca]>;
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtZcmp),
"'Zcmp' (sequenced instuctions for code-size reduction)">;
def FeatureStdExtZcmt
- : SubtargetFeature<"zcmt", "HasStdExtZcmt", "true",
- "'Zcmt' (table jump instuctions for code-size reduction)",
- [FeatureStdExtZca, FeatureStdExtZicsr]>;
+ : RISCVExtension<"zcmt", 1, 0, "HasStdExtZcmt", "true",
+ "'Zcmt' (table jump instuctions for code-size reduction)",
+ [FeatureStdExtZca, FeatureStdExtZicsr]>;
def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
AssemblerPredicate<(all_of FeatureStdExtZcmt),
"'Zcmt' (table jump instuctions for code-size reduction)">;
def FeatureStdExtZce
- : SubtargetFeature<"zce", "HasStdExtZce", "true",
- "'Zce' (Compressed extensions for microcontrollers)",
- [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
+ : RISCVExtension<"zce", 1, 0, "HasStdExtZce", "true",
+ "'Zce' (Compressed extensions for microcontrollers)",
+ [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
FeatureStdExtZcmt]>;
def HasStdExtCOrZcfOrZce
@@ -392,9 +406,9 @@ def HasStdExtCOrZcfOrZce
"'C' (Compressed Instructions) or "
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
-def FeatureStdExtZcmop : SubtargetFeature<"zcmop", "HasStdExtZcmop", "true",
- "'Zcmop' (Compressed May-Be-Operations)",
- [FeatureStdExtZca]>;
+def FeatureStdExtZcmop : RISCVExtension<"zcmop", 1, 0, "HasStdExtZcmop", "true",
+ "'Zcmop' (Compressed May-Be-Operations)",
+ [FeatureStdExtZca]>;
def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
AssemblerPredicate<(all_of FeatureStdExtZcmop),
"'Zcmop' (Compressed May-Be-Operations)">;
@@ -402,30 +416,30 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
// Bitmanip Extensions
def FeatureStdExtZba
- : SubtargetFeature<"zba", "HasStdExtZba", "true",
- "'Zba' (Address Generation Instructions)">;
+ : RISCVExtension<"zba", 1, 0, "HasStdExtZba", "true",
+ "'Zba' (Address Generation Instructions)">;
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
AssemblerPredicate<(all_of FeatureStdExtZba),
"'Zba' (Address Generation Instructions)">;
def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
def FeatureStdExtZbb
- : SubtargetFeature<"zbb", "HasStdExtZbb", "true",
- "'Zbb' (Basic Bit-Manipulation)">;
+ : RISCVExtension<"zbb", 1, 0, "HasStdExtZbb", "true",
+ "'Zbb' (Basic Bit-Manipulation)">;
def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
AssemblerPredicate<(all_of FeatureStdExtZbb),
"'Zbb' (Basic Bit-Manipulation)">;
def FeatureStdExtZbc
- : SubtargetFeature<"zbc", "HasStdExtZbc", "true",
- "'Zbc' (Carry-Less Multiplication)">;
+ : RISCVExtension<"zbc", 1, 0, "HasStdExtZbc", "true",
+ "'Zbc' (Carry-Less Multiplication)">;
def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
AssemblerPredicate<(all_of FeatureStdExtZbc),
"'Zbc' (Carry-Less Multiplication)">;
def FeatureStdExtZbs
- : SubtargetFeature<"zbs", "HasStdExtZbs", "true",
- "'Zbs' (Single-Bit Instructions)">;
+ : RISCVExtension<"zbs", 1, 0, "HasStdExtZbs", "true",
+ "'Zbs' (Single-Bit Instructions)">;
def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
AssemblerPredicate<(all_of FeatureStdExtZbs),
"'Zbs' (Single-Bit Instructions)">;
@@ -433,15 +447,15 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
// Bitmanip Extensions for Cryptography Extensions
def FeatureStdExtZbkb
- : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
- "'Zbkb' (Bitmanip instructions for Cryptography)">;
+ : RISCVExtension<"zbkb", 1, 0, "HasStdExtZbkb", "true",
+ "'Zbkb' (Bitmanip instructions for Cryptography)">;
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
AssemblerPredicate<(all_of FeatureStdExtZbkb),
"'Zbkb' (Bitmanip instructions for Cryptography)">;
def FeatureStdExtZbkx
- : SubtargetFeature<"zbkx", "HasStdExtZbkx", "true",
- "'Zbkx' (Crossbar permutation instructions)">;
+ : RISCVExtension<"zbkx", 1, 0, "HasStdExtZbkx", "true",
+ "'Zbkx' (Crossbar permutation instructions)">;
def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
AssemblerPredicate<(all_of FeatureStdExtZbkx),
"'Zbkx' (Crossbar permutation instructions)">;
@@ -456,9 +470,9 @@ def HasStdExtZbbOrZbkb
// carry-less multiply subextension. The former should be enabled if the latter
// is enabled.
def FeatureStdExtZbkc
- : SubtargetFeature<"zbkc", "HasStdExtZbkc", "true",
- "'Zbkc' (Carry-less multiply instructions for "
- "Cryptography)">;
+ : RISCVExtension<"zbkc", 1, 0, "HasStdExtZbkc", "true",
+ "'Zbkc' (Carry-less multiply instructions for "
+ "Cryptography)">;
def HasStdExtZbkc
: Predicate<"Subtarget->hasStdExtZbkc()">,
AssemblerPredicate<(all_of FeatureStdExtZbkc),
@@ -474,15 +488,15 @@ def HasStdExtZbcOrZbkc
// Cryptography Extensions
def FeatureStdExtZknd
- : SubtargetFeature<"zknd", "HasStdExtZknd", "true",
- "'Zknd' (NIST Suite: AES Decryption)">;
+ : RISCVExtension<"zknd", 1, 0, "HasStdExtZknd", "true",
+ "'Zknd' (NIST Suite: AES Decryption)">;
def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
AssemblerPredicate<(all_of FeatureStdExtZknd),
"'Zknd' (NIST Suite: AES Decryption)">;
def FeatureStdExtZkne
- : SubtargetFeature<"zkne", "HasStdExtZkne", "true",
- "'Zkne' (NIST Suite: AES Encryption)">;
+ : RISCVExtension<"zkne", 1, 0, "HasStdExtZkne", "true",
+ "'Zkne' (NIST Suite: AES Encryption)">;
def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
AssemblerPredicate<(all_of FeatureStdExtZkne),
"'Zkne' (NIST Suite: AES Encryption)">;
@@ -496,136 +510,136 @@ def HasStdExtZkndOrZkne
"'Zkne' (NIST Suite: AES Encryption)">;
def FeatureStdExtZknh
- : SubtargetFeature<"zknh", "HasStdExtZknh", "true",
- "'Zknh' (NIST Suite: Hash Function Instructions)">;
+ : RISCVExtension<"zknh", 1, 0, "HasStdExtZknh", "true",
+ "'Zknh' (NIST Suite: Hash Function Instructions)">;
def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
AssemblerPredicate<(all_of FeatureStdExtZknh),
"'Zknh' (NIST Suite: Hash Function Instructions)">;
def FeatureStdExtZksed
- : SubtargetFeature<"zksed", "HasStdExtZksed", "true",
- "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
+ : RISCVExtension<"zksed", 1, 0, "HasStdExtZksed", "true",
+ "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
AssemblerPredicate<(all_of FeatureStdExtZksed),
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
def FeatureStdExtZksh
- : SubtargetFeature<"zksh", "HasStdExtZksh", "true",
- "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
+ : RISCVExtension<"zksh", 1, 0, "HasStdExtZksh", "true",
+ "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
AssemblerPredicate<(all_of FeatureStdExtZksh),
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
def FeatureStdExtZkr
- : SubtargetFeature<"zkr", "HasStdExtZkr", "true",
- "'Zkr' (Entropy Source Extension)">;
+ : RISCVExtension<"zkr", 1, 0, "HasStdExtZkr", "true",
+ "'Zkr' (Entropy Source Extension)">;
def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
AssemblerPredicate<(all_of FeatureStdExtZkr),
"'Zkr' (Entropy Source Extension)">;
def FeatureStdExtZkn
- : SubtargetFeature<"zkn", "HasStdExtZkn", "true",
- "'Zkn' (NIST Algorithm Suite)",
- [FeatureStdExtZbkb,
- FeatureStdExtZbkc,
- FeatureStdExtZbkx,
- FeatureStdExtZkne,
- FeatureStdExtZknd,
- FeatureStdExtZknh]>;
+ : RISCVExtension<"zkn", 1, 0, "HasStdExtZkn", "true",
+ "'Zkn' (NIST Algorithm Suite)",
+ [FeatureStdExtZbkb,
+ FeatureStdExtZbkc,
+ FeatureStdExtZbkx,
+ FeatureStdExtZkne,
+ FeatureStdExtZknd,
+ FeatureStdExtZknh]>;
def FeatureStdExtZks
- : SubtargetFeature<"zks", "HasStdExtZks", "true",
- "'Zks' (ShangMi Algorithm Suite)",
- [FeatureStdExtZbkb,
- FeatureStdExtZbkc,
- FeatureStdExtZbkx,
- FeatureStdExtZksed,
- FeatureStdExtZksh]>;
+ : RISCVExtension<"zks", 1, 0, "HasStdExtZks", "true",
+ "'Zks' (ShangMi Algorithm Suite)",
+ [FeatureStdExtZbkb,
+ FeatureStdExtZbkc,
+ FeatureStdExtZbkx,
+ FeatureStdExtZksed,
+ FeatureStdExtZksh]>;
def FeatureStdExtZkt
- : SubtargetFeature<"zkt", "HasStdExtZkt", "true",
- "'Zkt' (Data Independent Execution Latency)">;
+ : RISCVExtension<"zkt", 1, 0, "HasStdExtZkt", "true",
+ "'Zkt' (Data Independent Execution Latency)">;
def FeatureStdExtZk
- : SubtargetFeature<"zk", "HasStdExtZk", "true",
- "'Zk' (Standard scalar cryptography extension)",
- [FeatureStdExtZkn,
- FeatureStdExtZkr,
- FeatureStdExtZkt]>;
+ : RISCVExtension<"zk", 1, 0, "HasStdExtZk", "true",
+ "'Zk' (Standard scalar cryptography extension)",
+ [FeatureStdExtZkn,
+ FeatureStdExtZkr,
+ FeatureStdExtZkt]>;
// Vector Extensions
-def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",
- "'Zvl' (Minimum Vector Length) 32">;
+def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0, "ZvlLen", "32",
+ "'Zvl' (Minimum Vector Length) 32">;
foreach i = { 6-16 } in {
defvar I = !shl(1, i);
def FeatureStdExtZvl#I#b :
- SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I),
- "'Zvl' (Minimum Vector Length) "#I,
- [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
+ RISCVExtension<"zvl"#I#"b", 1, 0, "ZvlLen", !cast<string>(I),
+ "'Zvl' (Minimum Vector Length) "#I,
+ [!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
}
def FeatureStdExtZve32x
- : SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
- "'Zve32x' (Vector Extensions for Embedded Processors "
- "with maximal 32 EEW)",
- [FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
+ : RISCVExtension<"zve32x", 1, 0, "HasStdExtZve32x", "true",
+ "'Zve32x' (Vector Extensions for Embedded Processors "
+ "with maximal 32 EEW)",
+ [FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
def FeatureStdExtZve32f
- : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
- "'Zve32f' (Vector Extensions for Embedded Processors "
- "with maximal 32 EEW and F extension)",
- [FeatureStdExtZve32x, FeatureStdExtF]>;
+ : RISCVExtension<"zve32f", 1, 0, "HasStdExtZve32f", "true",
+ "'Zve32f' (Vector Extensions for Embedded Processors "
+ "with maximal 32 EEW and F extension)",
+ [FeatureStdExtZve32x, FeatureStdExtF]>;
def FeatureStdExtZve64x
- : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
- "'Zve64x' (Vector Extensions for Embedded Processors "
- "with maximal 64 EEW)",
- [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
+ : RISCVExtension<"zve64x", 1, 0, "HasStdExtZve64x", "true",
+ "'Zve64x' (Vector Extensions for Embedded Processors "
+ "with maximal 64 EEW)",
+ [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
def FeatureStdExtZve64f
- : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
- "'Zve64f' (Vector Extensions for Embedded Processors "
- "with maximal 64 EEW and F extension)",
- [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
+ : RISCVExtension<"zve64f", 1, 0, "HasStdExtZve64f", "true",
+ "'Zve64f' (Vector Extensions for Embedded Processors "
+ "with maximal 64 EEW and F extension)",
+ [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
def FeatureStdExtZve64d
- : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
- "'Zve64d' (Vector Extensions for Embedded Processors "
- "with maximal 64 EEW, F and D extension)",
- [FeatureStdExtZve64f, FeatureStdExtD]>;
+ : RISCVExtension<"zve64d", 1, 0, "HasStdExtZve64d", "true",
+ "'Zve64d' (Vector Extensions for Embedded Processors "
+ "with maximal 64 EEW, F and D extension)",
+ [FeatureStdExtZve64f, FeatureStdExtD]>;
def FeatureStdExtV
- : SubtargetFeature<"v", "HasStdExtV", "true",
- "'V' (Vector Extension for Application Processors)",
- [FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
+ : RISCVExtension<"v", 1, 0, "HasStdExtV", "true",
+ "'V' (Vector Extension for Application Processors)",
+ [FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
def FeatureStdExtZvfbfmin
- : SubtargetFeature<"experimental-zvfbfmin", "HasStdExtZvfbfmin", "true",
- "'Zvbfmin' (Vector BF16 Converts)",
- [FeatureStdExtZve32f]>;
+ : RISCVExperimentalExtension<"zvfbfmin", 1, 0, "HasStdExtZvfbfmin", "true",
+ "'Zvbfmin' (Vector BF16 Converts)",
+ [FeatureStdExtZve32f]>;
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
"'Zvfbfmin' (Vector BF16 Converts)">;
def FeatureStdExtZvfbfwma
- : SubtargetFeature<"experimental-zvfbfwma", "HasStdExtZvfbfwma", "true",
- "'Zvfbfwma' (Vector BF16 widening mul-add)",
- [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
+ : RISCVExperimentalExtension<"zvfbfwma", 1, 0, "HasStdExtZvfbfwma", "true",
+ "'Zvfbfwma' (Vector BF16 widening mul-add)",
+ [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
def FeatureStdExtZvfhmin
- : SubtargetFeature<"zvfhmin", "HasStdExtZvfhmin", "true",
- "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
- [FeatureStdExtZve32f]>;
+ : RISCVExtension<"zvfhmin", 1, 0, "HasStdExtZvfhmin", "true",
+ "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
+ [FeatureStdExtZve32f]>;
def FeatureStdExtZvfh
- : SubtargetFeature<"zvfh", "HasStdExtZvfh", "true",
- "'Zvfh' (Vector Half-Precision Floating-Point)",
- [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>;
+ : RISCVExtension<"zvfh", 1, 0, "HasStdExtZvfh", "true",
+ "'Zvfh' (Vector Half-Precision Floating-Point)",
+ [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>;
def HasStdExtZfhOrZvfh
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
@@ -636,52 +650,52 @@ def HasStdExtZfhOrZvfh
// Vector Cryptography and Bitmanip Extensions
def FeatureStdExtZvkb
- : SubtargetFeature<"zvkb", "HasStdExtZvkb", "true",
- "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
+ : RISCVExtension<"zvkb", 1, 0, "HasStdExtZvkb", "true",
+ "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
AssemblerPredicate<(all_of FeatureStdExtZvkb),
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
def FeatureStdExtZvbb
- : SubtargetFeature<"zvbb", "HasStdExtZvbb", "true",
- "'Zvbb' (Vector basic bit-manipulation instructions)",
- [FeatureStdExtZvkb]>;
+ : RISCVExtension<"zvbb", 1, 0, "HasStdExtZvbb", "true",
+ "'Zvbb' (Vector basic bit-manipulation instructions)",
+ [FeatureStdExtZvkb]>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
AssemblerPredicate<(all_of FeatureStdExtZvbb),
"'Zvbb' (Vector basic bit-manipulation instructions)">;
def FeatureStdExtZvbc
- : SubtargetFeature<"zvbc", "HasStdExtZvbc", "true",
- "'Zvbc' (Vector Carryless Multiplication)">;
+ : RISCVExtension<"zvbc", 1, 0, "HasStdExtZvbc", "true",
+ "'Zvbc' (Vector Carryless Multiplication)">;
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
AssemblerPredicate<(all_of FeatureStdExtZvbc),
"'Zvbc' (Vector Carryless Multiplication)">;
def FeatureStdExtZvkg
- : SubtargetFeature<"zvkg", "HasStdExtZvkg", "true",
- "'Zvkg' (Vector GCM instructions for Cryptography)">;
+ : RISCVExtension<"zvkg", 1, 0, "HasStdExtZvkg", "true",
+ "'Zvkg' (Vector GCM instructions for Cryptography)">;
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
AssemblerPredicate<(all_of FeatureStdExtZvkg),
"'Zvkg' (Vector GCM instructions for Cryptography)">;
def FeatureStdExtZvkned
- : SubtargetFeature<"zvkned", "HasStdExtZvkned", "true",
- "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
+ : RISCVExtension<"zvkned", 1, 0, "HasStdExtZvkned", "true",
+ "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
AssemblerPredicate<(all_of FeatureStdExtZvkned),
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
def FeatureStdExtZvknha
- : SubtargetFeature<"zvknha", "HasStdExtZvknha", "true",
- "'Zvknha' (Vector SHA-2 (SHA-256 only))">;
+ : RISCVExtension<"zvknha", 1, 0, "HasStdExtZvknha", "true",
+ "'Zvknha' (Vector SHA-2 (SHA-256 only))">;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
def FeatureStdExtZvknhb
- : SubtargetFeature<"zvknhb", "HasStdExtZvknhb", "true",
- "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
- [FeatureStdExtZve64x]>;
+ : RISCVExtension<"zvknhb", 1, 0, "HasStdExtZvknhb", "true",
+ "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
+ [FeatureStdExtZve64x]>;
def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
AssemblerPredicate<(all_of FeatureStdExtZvknhb),
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
@@ -691,58 +705,58 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg
"'Zvknha' or 'Zvknhb' (Vector SHA-2)">;
def FeatureStdExtZvksed
- : SubtargetFeature<"zvksed", "HasStdExtZvksed", "true",
- "'Zvksed' (SM4 Block Cipher Instructions)">;
+ : RISCVExtension<"zvksed", 1, 0, "HasStdExtZvksed", "true",
+ "'Zvksed' (SM4 Block Cipher Instructions)">;
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions)">;
def FeatureStdExtZvksh
- : SubtargetFeature<"zvksh", "HasStdExtZvksh", "true",
- "'Zvksh' (SM3 Hash Function Instructions)">;
+ : RISCVExtension<"zvksh", 1, 0, "HasStdExtZvksh", "true",
+ "'Zvksh' (SM3 Hash Function Instructions)">;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions)">;
def FeatureStdExtZvkt
- : SubtargetFeature<"zvkt", "HasStdExtZvkt", "true",
- "'Zvkt' (Vector Data-Independent Execution Latency)">;
+ : RISCVExtension<"zvkt", 1, 0, "HasStdExtZvkt", "true",
+ "'Zvkt' (Vector Data-Independent Execution Latency)">;
// Zvk short-hand extensions
def FeatureStdExtZvkn
- : SubtargetFeature<"zvkn", "HasStdExtZvkn", "true",
- "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and "
- "'Zvkt')",
- [FeatureStdExtZvkned, FeatureStdExtZvknhb,
- FeatureStdExtZvkb, FeatureStdExtZvkt]>;
+ : RISCVExtension<"zvkn", 1, 0, "HasStdExtZvkn", "true",
+ "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and "
+ "'Zvkt')",
+ [FeatureStdExtZvkned, FeatureStdExtZvknhb,
+ FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvknc
- : SubtargetFeature<"zvknc", "HasStdExtZvknc", "true",
- "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
- [FeatureStdExtZvkn, FeatureStdExtZvbc]>;
+ : RISCVExtension<"zvknc", 1, 0, "HasStdExtZvknc", "true",
+ "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
+ [FeatureStdExtZvkn, FeatureStdExtZvbc]>;
def FeatureStdExtZvkng
- : SubtargetFeature<"zvkng", "HasStdExtZvkng", "true",
- "'zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
- [FeatureStdExtZvkn, FeatureStdExtZvkg]>;
+ : RISCVExtension<"zvkng", 1, 0, "HasStdExtZvkng", "true",
+ "'zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
+ [FeatureStdExtZvkn, FeatureStdExtZvkg]>;
def FeatureStdExtZvks
- : SubtargetFeature<"zvks", "HasStdExtZvks", "true",
- "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and "
- "'Zvkt')",
- [FeatureStdExtZvksed, FeatureStdExtZvksh,
- FeatureStdExtZvkb, FeatureStdExtZvkt]>;
+ : RISCVExtension<"zvks", 1, 0, "HasStdExtZvks", "true",
+ "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and "
+ "'Zvkt')",
+ [FeatureStdExtZvksed, FeatureStdExtZvksh,
+ FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvksc
- : SubtargetFeature<"zvksc", "HasStdExtZvksc", "true",
- "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
- [FeatureStdExtZvks, FeatureStdExtZvbc]>;
+ : RISCVExtension<"zvksc", 1, 0, "HasStdExtZvksc", "true",
+ "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
+ [FeatureStdExtZvks, FeatureStdExtZvbc]>;
def FeatureStdExtZvksg
- : SubtargetFeature<"zvksg", "HasStdExtZvksg", "true",
- "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
- [FeatureStdExtZvks, FeatureStdExtZvkg]>;
+ : RISCVExtension<"zvksg", 1, 0, "HasStdExtZvksg", "true",
+ "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
+ [FeatureStdExtZvks, FeatureStdExtZvkg]>;
// Vector instruction predicates
@@ -776,8 +790,8 @@ def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMul
// Hypervisor Extensions
def FeatureStdExtH
- : SubtargetFeature<"h", "HasStdExtH", "true",
- "'H' (Hypervisor)">;
+ : RISCVExtension<"h", 1, 0, "HasStdExtH", "true",
+ "'H' (Hypervisor)">;
def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
AssemblerPredicate<(all_of FeatureStdExtH),
@@ -786,105 +800,104 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
// Supervisor extensions
def FeatureStdExtShgatpa
- : SubtargetFeature<"shgatpa", "HasStdExtShgatpa", "true",
- "'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)", []>;
+ : RISCVExtension<"shgatpa", 1, 0, "HasStdExtShgatpa", "true",
+ "'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)">;
def FeatureStdExtShvsatpa
- : SubtargetFeature<"shvsatpa", "HasStdExtSvsatpa", "true",
- "'Svsatpa' (vsatp supports all modes supported by satp)", []>;
+ : RISCVExtension<"shvsatpa", 1, 0, "HasStdExtSvsatpa", "true",
+ "'Svsatpa' (vsatp supports all modes supported by satp)">;
def FeatureStdExtSmaia
- : SubtargetFeature<"smaia", "HasStdExtSmaia", "true",
- "'Smaia' (Advanced Interrupt Architecture Machine "
- "Level)", []>;
+ : RISCVExtension<"smaia", 1, 0, "HasStdExtSmaia", "true",
+ "'Smaia' (Advanced Interrupt Architecture Machine Level)">;
def FeatureStdExtSsaia
- : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
+ : RISCVExtension<"ssaia", 1, 0, "HasStdExtSsaia", "true",
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
- "Level)", []>;
+ "Level)">;
def FeatureStdExtSmepmp
- : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
- "'Smepmp' (Enhanced Physical Memory Protection)", []>;
+ : RISCVExtension<"smepmp", 1, 0, "HasStdExtSmepmp", "true",
+ "'Smepmp' (Enhanced Physical Memory Protection)">;
def FeatureStdExtSsccptr
- : SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true",
- "'Ssccptr' (Main memory supports page table reads)", []>;
+ : RISCVExtension<"ssccptr", 1, 0, "HasStdExtSsccptr", "true",
+ "'Ssccptr' (Main memory supports page table reads)">;
def FeatureStdExtSscofpmf
- : SubtargetFeature<"sscofpmf", "HasStdExtSscofpmf", "true",
- "'Sscofpmf' (Count Overflow and Mode-Based Filtering)", []>;
+ : RISCVExtension<"sscofpmf", 1, 0, "HasStdExtSscofpmf", "true",
+ "'Sscofpmf' (Count Overflow and Mode-Based Filtering)">;
def FeatureStdExtShcounterenw
- : SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true",
- "'Shcounterenw' (Support writeable hcounteren enable "
- "bit for any hpmcounter that is not read-only zero)", []>;
+ : RISCVExtension<"shcounterenw", 1, 0, "HasStdExtShcounterenw", "true",
+ "'Shcounterenw' (Support writeable hcounteren enable "
+ "bit for any hpmcounter that is not read-only zero)">;
def FeatureStdExtSscounterenw
- : SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true",
- "'Sscounterenw' (Support writeable scounteren enable "
- "bit for any hpmcounter that is not read-only zero)", []>;
+ : RISCVExtension<"sscounterenw", 1, 0, "HasStdExtSscounterenw", "true",
+ "'Sscounterenw' (Support writeable scounteren enable "
+ "bit for any hpmcounter that is not read-only zero)">;
def FeatureStdExtSsstateen
- : SubtargetFeature<"ssstateen", "HasStdExtSsstateen", "true",
- "'Ssstateen' (Supervisor-mode view of the state-enable extension)", []>;
+ : RISCVExtension<"ssstateen", 1, 0, "HasStdExtSsstateen", "true",
+ "'Ssstateen' (Supervisor-mode view of the state-enable extension)">;
def FeatureStdExtSsstrict
- : SubtargetFeature<"ssstrict", "HasStdExtSsstrict", "true",
- "'Ssstrict' (No non-conforming extensions are present)", []>;
+ : RISCVExtension<"ssstrict", 1, 0, "HasStdExtSsstrict", "true",
+ "'Ssstrict' (No non-conforming extensions are present)">;
def FeatureStdExtSstc
- : SubtargetFeature<"sstc", "HasStdExtSstc", "true",
- "'Sstc' (Supervisor-mode timer interrupts)", []>;
+ : RISCVExtension<"sstc", 1, 0, "HasStdExtSstc", "true",
+ "'Sstc' (Supervisor-mode timer interrupts)">;
def FeaturesSsqosid
- : SubtargetFeature<"experimental-ssqosid", "HasStdExtSsqosid", "true",
- "'Ssqosid' (Quality-of-Service (QoS) Identifiers)", []>;
+ : RISCVExperimentalExtension<"ssqosid", 1, 0, "HasStdExtSsqosid", "true",
+ "'Ssqosid' (Quality-of-Service (QoS) Identifiers)">;
def FeatureStdExtShtvala
- : SubtargetFeature<"shtvala", "HasStdExtShtvala", "true",
- "'Shtvala' (htval provides all needed values)", []>;
+ : RISCVExtension<"shtvala", 1, 0, "HasStdExtShtvala", "true",
+ "'Shtvala' (htval provides all needed values)">;
def FeatureStdExtShvstvala
- : SubtargetFeature<"shvstvala", "HasStdExtShvstvala", "true",
- "'Shvstvala' (vstval provides all needed values)", []>;
+ : RISCVExtension<"shvstvala", 1, 0, "HasStdExtShvstvala", "true",
+ "'Shvstvala' (vstval provides all needed values)">;
def FeatureStdExtSstvala
- : SubtargetFeature<"sstvala", "HasStdExtSstvala", "true",
- "'Sstvala' (stval provides all needed values)", []>;
+ : RISCVExtension<"sstvala", 1, 0, "HasStdExtSstvala", "true",
+ "'Sstvala' (stval provides all needed values)">;
def FeatureStdExtShvstvecd
- : SubtargetFeature<"shvstvecd", "HasStdExtShvstvecd", "true",
- "'Shvstvecd' (vstvec supports Direct mode)", []>;
+ : RISCVExtension<"shvstvecd", 1, 0, "HasStdExtShvstvecd", "true",
+ "'Shvstvecd' (vstvec supports Direct mode)">;
def FeatureStdExtSstvecd
- : SubtargetFeature<"sstvecd", "HasStdExtSstvecd", "true",
- "'Sstvecd' (stvec supports Direct mode)", []>;
+ : RISCVExtension<"sstvecd", 1, 0, "HasStdExtSstvecd", "true",
+ "'Sstvecd' (stvec supports Direct mode)">;
def FeatureStdExtSsu64xl
- : SubtargetFeature<"ssu64xl", "HasStdExtSsu64xl", "true",
- "'Ssu64xl' (UXLEN=64 supported)", []>;
+ : RISCVExtension<"ssu64xl", 1, 0, "HasStdExtSsu64xl", "true",
+ "'Ssu64xl' (UXLEN=64 supported)">;
def FeatureStdExtSvade
- : SubtargetFeature<"svade", "HasStdExtSvade", "true",
- "'Svade' (Raise exceptions on improper A/D bits)", []>;
+ : RISCVExtension<"svade", 1, 0, "HasStdExtSvade", "true",
+ "'Svade' (Raise exceptions on improper A/D bits)">;
def FeatureStdExtSvadu
- : SubtargetFeature<"svadu", "HasStdExtSvadu", "true",
- "'Svadu' (Hardware A/D updates)", []>;
+ : RISCVExtension<"svadu", 1, 0, "HasStdExtSvadu", "true",
+ "'Svadu' (Hardware A/D updates)">;
def FeatureStdExtSvbare
- : SubtargetFeature<"svbare", "HasStdExtSvbare", "true",
- "'Svbare' $(satp mode Bare supported)", []>;
+ : RISCVExtension<"svbare", 1, 0, "HasStdExtSvbare", "true",
+ "'Svbare' $(satp mode Bare supported)">;
def FeatureStdExtSvinval
- : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
- "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
+ : RISCVExtension<"svinval", 1, 0, "HasStdExtSvinval", "true",
+ "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
AssemblerPredicate<(all_of FeatureStdExtSvinval),
"'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
def FeatureStdExtSvnapot
- : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
- "'Svnapot' (NAPOT Translation Contiguity)">;
+ : RISCVExtension<"svnapot", 1, 0, "HasStdExtSvnapot", "true",
+ "'Svnapot' (NAPOT Translation Contiguity)">;
def FeatureStdExtSvpbmt
- : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
- "'Svpbmt' (Page-Based Memory Types)">;
+ : RISCVExtension<"svpbmt", 1, 0, "HasStdExtSvpbmt", "true",
+ "'Svpbmt' (Page-Based Memory Types)">;
// Pointer Masking extensions
@@ -892,33 +905,33 @@ def FeatureStdExtSvpbmt
// privilege mode (U-mode), and for VS- and VU-modes if the H extension is
// present.
def FeatureStdExtSsnpm
- : SubtargetFeature<"experimental-ssnpm", "HasStdExtSsnpm", "true",
- "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
+ : RISCVExperimentalExtension<"ssnpm", 0, 8, "HasStdExtSsnpm", "true",
+ "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
// A machine-level extension that provides pointer masking for the next lower
// privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
def FeatureStdExtSmnpm
- : SubtargetFeature<"experimental-smnpm", "HasStdExtSmnpm", "true",
- "'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">;
+ : RISCVExperimentalExtension<"smnpm", 0, 8, "HasStdExtSmnpm", "true",
+ "'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">;
// A machine-level extension that provides pointer masking for M-mode.
def FeatureStdExtSmmpm
- : SubtargetFeature<"experimental-smmpm", "HasStdExtSmmpm", "true",
- "'Smmpm' (Machine-level Pointer Masking for M-mode)">;
+ : RISCVExperimentalExtension<"smmpm", 0, 8, "HasStdExtSmmpm", "true",
+ "'Smmpm' (Machine-level Pointer Masking for M-mode)">;
// An extension that indicates that there is pointer-masking support available
// in supervisor mode, with some facility provided in the supervisor execution
// environment to control pointer masking.
def FeatureStdExtSspm
- : SubtargetFeature<"experimental-sspm", "HasStdExtSspm", "true",
- "'Sspm' (Indicates Supervisor-mode Pointer Masking)">;
+ : RISCVExperimentalExtension<"sspm", 0, 8, "HasStdExtSspm", "true",
+ "'Sspm' (Indicates Supervisor-mode Pointer Masking)">;
// An extension that indicates that there is pointer-masking support available
// in user mode, with some facility provided in the application execution
// environment to control pointer masking.
def FeatureStdExtSupm
- : SubtargetFeature<"experimental-supm", "HasStdExtSupm", "true",
- "'Supm' (Indicates User-mode Pointer Masking)">;
+ : RISCVExperimentalExtension<"supm", 0, 8, "HasStdExtSupm", "true",
+ "'Supm' (Indicates User-mode Pointer Masking)">;
//===----------------------------------------------------------------------===//
// Vendor extensions
@@ -927,8 +940,8 @@ def FeatureStdExtSupm
// Ventana Extenions
def FeatureVendorXVentanaCondOps
- : SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true",
- "'XVentanaCondOps' (Ventana Conditional Ops)">;
+ : RISCVExtension<"xventanacondops", 1, 0, "HasVendorXVentanaCondOps", "true",
+ "'XVentanaCondOps' (Ventana Conditional Ops)">;
def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
"'XVentanaCondOps' (Ventana Conditional Ops)">;
@@ -936,80 +949,80 @@ def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()"
// T-Head Extensions
def FeatureVendorXTHeadBa
- : SubtargetFeature<"xtheadba", "HasVendorXTHeadBa", "true",
- "'xtheadba' (T-Head address calculation instructions)">;
+ : RISCVExtension<"xtheadba", 1, 0, "HasVendorXTHeadBa", "true",
+ "'xtheadba' (T-Head address calculation instructions)">;
def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadBa),
"'xtheadba' (T-Head address calculation instructions)">;
def FeatureVendorXTHeadBb
- : SubtargetFeature<"xtheadbb", "HasVendorXTHeadBb", "true",
- "'xtheadbb' (T-Head basic bit-manipulation instructions)">;
+ : RISCVExtension<"xtheadbb", 1, 0, "HasVendorXTHeadBb", "true",
+ "'xtheadbb' (T-Head basic bit-manipulation instructions)">;
def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadBb),
"'xtheadbb' (T-Head basic bit-manipulation instructions)">;
def FeatureVendorXTHeadBs
- : SubtargetFeature<"xtheadbs", "HasVendorXTHeadBs", "true",
- "'xtheadbs' (T-Head single-bit instructions)">;
+ : RISCVExtension<"xtheadbs", 1, 0, "HasVendorXTHeadBs", "true",
+ "'xtheadbs' (T-Head single-bit instructions)">;
def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadBs),
"'xtheadbs' (T-Head single-bit instructions)">;
def FeatureVendorXTHeadCondMov
- : SubtargetFeature<"xtheadcondmov", "HasVendorXTHeadCondMov", "true",
- "'xtheadcondmov' (T-Head conditional move instructions)">;
+ : RISCVExtension<"xtheadcondmov", 1, 0, "HasVendorXTHeadCondMov", "true",
+ "'xtheadcondmov' (T-Head conditional move instructions)">;
def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov),
"'xtheadcondmov' (T-Head conditional move instructions)">;
def FeatureVendorXTHeadCmo
- : SubtargetFeature<"xtheadcmo", "HasVendorXTHeadCmo", "true",
- "'xtheadcmo' (T-Head cache management instructions)">;
+ : RISCVExtension<"xtheadcmo", 1, 0, "HasVendorXTHeadCmo", "true",
+ "'xtheadcmo' (T-Head cache management instructions)">;
def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadCmo),
"'xtheadcmo' (T-Head cache management instructions)">;
def FeatureVendorXTHeadFMemIdx
- : SubtargetFeature<"xtheadfmemidx", "HasVendorXTHeadFMemIdx", "true",
- "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)",
- [FeatureStdExtF]>;
+ : RISCVExtension<"xtheadfmemidx", 1, 0, "HasVendorXTHeadFMemIdx", "true",
+ "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)",
+ [FeatureStdExtF]>;
def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx),
"'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">;
def FeatureVendorXTHeadMac
- : SubtargetFeature<"xtheadmac", "HasVendorXTHeadMac", "true",
- "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
+ : RISCVExtension<"xtheadmac", 1, 0, "HasVendorXTHeadMac", "true",
+ "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadMac),
"'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
def FeatureVendorXTHeadMemIdx
- : SubtargetFeature<"xtheadmemidx", "HasVendorXTHeadMemIdx", "true",
- "'xtheadmemidx' (T-Head Indexed Memory Operations)">;
+ : RISCVExtension<"xtheadmemidx", 1, 0, "HasVendorXTHeadMemIdx", "true",
+ "'xtheadmemidx' (T-Head Indexed Memory Operations)">;
def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx),
"'xtheadmemidx' (T-Head Indexed Memory Operations)">;
def FeatureVendorXTHeadMemPair
- : SubtargetFeature<"xtheadmempair", "HasVendorXTHeadMemPair", "true",
- "'xtheadmempair' (T-Head two-GPR Memory Operations)">;
+ : RISCVExtension<"xtheadmempair", 1, 0, "HasVendorXTHeadMemPair", "true",
+ "'xtheadmempair' (T-Head two-GPR Memory Operations)">;
def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair),
"'xtheadmempair' (T-Head two-GPR Memory Operations)">;
def FeatureVendorXTHeadSync
- : SubtargetFeature<"xtheadsync", "HasVendorXTHeadSync", "true",
- "'xtheadsync' (T-Head multicore synchronization instructions)">;
+ : RISCVExtension<"xtheadsync", 1, 0, "HasVendorXTHeadSync", "true",
+ "'xtheadsync' (T-Head multicore synchronization instructions)">;
def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadSync),
"'xtheadsync' (T-Head multicore synchronization instructions)">;
def FeatureVendorXTHeadVdot
- : SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true",
- "'xtheadvdot' (T-Head Vector Extensions for Dot)",
- [FeatureStdExtV]>;
+ : RISCVExtension<"xtheadvdot", 1, 0, "HasVendorXTHeadVdot", "true",
+ "'xtheadvdot' (T-Head Vector Extensions for Dot)",
+ [FeatureStdExtV]>;
def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
"'xtheadvdot' (T-Head Vector Extensions for Dot)">;
@@ -1017,68 +1030,68 @@ def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
// SiFive Extensions
def FeatureVendorXSfvcp
- : SubtargetFeature<"xsfvcp", "HasVendorXSfvcp", "true",
- "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
- [FeatureStdExtZve32x]>;
+ : RISCVExtension<"xsfvcp", 1, 0, "HasVendorXSfvcp", "true",
+ "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
+ [FeatureStdExtZve32x]>;
def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
AssemblerPredicate<(all_of FeatureVendorXSfvcp),
"'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">;
def FeatureVendorXSfvqmaccdod
- : SubtargetFeature<"xsfvqmaccdod", "HasVendorXSfvqmaccdod", "true",
- "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
- [FeatureStdExtZve32x]>;
+ : RISCVExtension<"xsfvqmaccdod", 1, 0, "HasVendorXSfvqmaccdod", "true",
+ "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
+ [FeatureStdExtZve32x]>;
def HasVendorXSfvqmaccdod
: Predicate<"Subtarget->hasVendorXSfvqmaccdod()">,
AssemblerPredicate<(all_of FeatureVendorXSfvqmaccdod),
"'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))">;
def FeatureVendorXSfvqmaccqoq
- : SubtargetFeature<"xsfvqmaccqoq", "HasVendorXSfvqmaccqoq", "true",
- "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",
- [FeatureStdExtZve32x]>;
+ : RISCVExtension<"xsfvqmaccqoq", 1, 0, "HasVendorXSfvqmaccqoq", "true",
+ "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",
+ [FeatureStdExtZve32x]>;
def HasVendorXSfvqmaccqoq
: Predicate<"Subtarget->hasVendorXSfvqmaccqoq()">,
AssemblerPredicate<(all_of FeatureVendorXSfvqmaccqoq),
"'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))">;
def FeatureVendorXSfvfwmaccqqq
- : SubtargetFeature<"xsfvfwmaccqqq", "HasVendorXSfvfwmaccqqq", "true",
- "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))",
- [FeatureStdExtZve32f, FeatureStdExtZvfbfmin]>;
+ : RISCVExtension<"xsfvfwmaccqqq", 1, 0, "HasVendorXSfvfwmaccqqq", "true",
+ "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))",
+ [FeatureStdExtZve32f, FeatureStdExtZvfbfmin]>;
def HasVendorXSfvfwmaccqqq
: Predicate<"Subtarget->hasVendorXSfvfwmaccqqq()">,
AssemblerPredicate<(all_of FeatureVendorXSfvfwmaccqqq),
"'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))">;
def FeatureVendorXSfvfnrclipxfqf
- : SubtargetFeature<"xsfvfnrclipxfqf", "HasVendorXSfvfnrclipxfqf", "true",
- "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",
- [FeatureStdExtZve32f]>;
+ : RISCVExtension<"xsfvfnrclipxfqf", 1, 0, "HasVendorXSfvfnrclipxfqf", "true",
+ "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",
+ [FeatureStdExtZve32f]>;
def HasVendorXSfvfnrclipxfqf
: Predicate<"Subtarget->hasVendorXSfvfnrclipxfqf()">,
AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),
"'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
def FeatureVendorXSiFivecdiscarddlone
- : SubtargetFeature<"xsifivecdiscarddlone", "HasVendorXSiFivecdiscarddlone", "true",
- "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)", []>;
+ : RISCVExtension<"xsifivecdiscarddlone", 1, 0, "HasVendorXSiFivecdiscarddlone", "true",
+ "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)", []>;
def HasVendorXSiFivecdiscarddlone
: Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">,
AssemblerPredicate<(all_of FeatureVendorXSiFivecdiscarddlone),
"'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)">;
def FeatureVendorXSiFivecflushdlone
- : SubtargetFeature<"xsifivecflushdlone", "HasVendorXSiFivecflushdlone", "true",
- "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)", []>;
+ : RISCVExtension<"xsifivecflushdlone", 1, 0, "HasVendorXSiFivecflushdlone", "true",
+ "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)", []>;
def HasVendorXSiFivecflushdlone
: Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">,
AssemblerPredicate<(all_of FeatureVendorXSiFivecflushdlone),
"'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)">;
def FeatureVendorXSfcease
- : SubtargetFeature<"xsfcease", "HasVendorXSfcease", "true",
- "'XSfcease' (SiFive sf.cease Instruction)", []>;
+ : RISCVExtension<"xsfcease", 1, 0, "HasVendorXSfcease", "true",
+ "'XSfcease' (SiFive sf.cease Instruction)", []>;
def HasVendorXSfcease
: Predicate<"Subtarget->hasVendorXSfcease()">,
AssemblerPredicate<(all_of FeatureVendorXSfcease),
@@ -1087,56 +1100,56 @@ def HasVendorXSfcease
// Core-V Extensions
def FeatureVendorXCVelw
- : SubtargetFeature<"xcvelw", "HasVendorXCVelw", "true",
- "'XCVelw' (CORE-V Event Load Word)">;
+ : RISCVExtension<"xcvelw", 1, 0, "HasVendorXCVelw", "true",
+ "'XCVelw' (CORE-V Event Load Word)">;
def HasVendorXCVelw
: Predicate<"Subtarget->hasVendorXCVelw()">,
AssemblerPredicate<(any_of FeatureVendorXCVelw),
"'XCVelw' (CORE-V Event Load Word)">;
def FeatureVendorXCVbitmanip
- : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true",
- "'XCVbitmanip' (CORE-V Bit Manipulation)">;
+ : RISCVExtension<"xcvbitmanip", 1, 0, "HasVendorXCVbitmanip", "true",
+ "'XCVbitmanip' (CORE-V Bit Manipulation)">;
def HasVendorXCVbitmanip
: Predicate<"Subtarget->hasVendorXCVbitmanip()">,
AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
"'XCVbitmanip' (CORE-V Bit Manipulation)">;
def FeatureVendorXCVmac
- : SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true",
- "'XCVmac' (CORE-V Multiply-Accumulate)">;
+ : RISCVExtension<"xcvmac", 1, 0, "HasVendorXCVmac", "true",
+ "'XCVmac' (CORE-V Multiply-Accumulate)">;
def HasVendorXCVmac
: Predicate<"Subtarget->hasVendorXCVmac()">,
AssemblerPredicate<(all_of FeatureVendorXCVmac),
"'XCVmac' (CORE-V Multiply-Accumulate)">;
def FeatureVendorXCVmem
- : SubtargetFeature<"xcvmem", "HasVendorXCVmem", "true",
- "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
+ : RISCVExtension<"xcvmem", 1, 0, "HasVendorXCVmem", "true",
+ "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
def HasVendorXCVmem
: Predicate<"Subtarget->hasVendorXCVmem()">,
AssemblerPredicate<(any_of FeatureVendorXCVmem),
"'XCVmem' (CORE-V Post-incrementing Load & Store)">;
def FeatureVendorXCValu
- : SubtargetFeature<"xcvalu", "HasVendorXCValu", "true",
- "'XCValu' (CORE-V ALU Operations)">;
+ : RISCVExtension<"xcvalu", 1, 0, "HasVendorXCValu", "true",
+ "'XCValu' (CORE-V ALU Operations)">;
def HasVendorXCValu
: Predicate<"Subtarget->hasVendorXCValu()">,
AssemblerPredicate<(all_of FeatureVendorXCValu),
"'XCValu' (CORE-V ALU Operations)">;
def FeatureVendorXCVsimd
- : SubtargetFeature<"xcvsimd", "HasVendorXCvsimd", "true",
- "'XCVsimd' (CORE-V SIMD ALU)">;
+ : RISCVExtension<"xcvsimd", 1, 0, "HasVendorXCvsimd", "true",
+ "'XCVsimd' (CORE-V SIMD ALU)">;
def HasVendorXCVsimd
: Predicate<"Subtarget->hasVendorXCVsimd()">,
AssemblerPredicate<(any_of FeatureVendorXCVsimd),
"'XCVsimd' (CORE-V SIMD ALU)">;
def FeatureVendorXCVbi
- : SubtargetFeature<"xcvbi", "HasVendorXCVbi", "true",
- "'XCVbi' (CORE-V Immediate Branching)">;
+ : RISCVExtension<"xcvbi", 1, 0, "HasVendorXCVbi", "true",
+ "'XCVbi' (CORE-V Immediate Branching)">;
def HasVendorXCVbi
: Predicate<"Subtarget->hasVendorXCVbi()">,
AssemblerPredicate<(all_of FeatureVendorXCVbi),
>From 616c474c6e4d64bee1e3b875a8a2037b1be5a914 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 19 Apr 2024 15:01:22 -0700
Subject: [PATCH 2/7] Fix indentation
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index b9034e7236b41b..2a28ff593402d3 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -106,7 +106,7 @@ def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0, "HasStdExtZihintntl", "true",
- "'Zihintntl' (Non-Temporal Locality Hints)">;
+ "'Zihintntl' (Non-Temporal Locality Hints)">;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -182,7 +182,7 @@ def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0, "HasStdExtZa128rs", "
def FeatureStdExtZaamo
: RISCVExperimentalExtension<"zaamo", 0, 2, "HasStdExtZaamo", "true",
- "'Zaamo' (Atomic Memory Operations)">;
+ "'Zaamo' (Atomic Memory Operations)">;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -368,8 +368,8 @@ def FeatureStdExtZcd
def HasStdExtCOrZcd
: Predicate<"Subtarget->hasStdExtCOrZcd()">,
AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
- "'C' (Compressed Instructions) or "
- "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
+ "'C' (Compressed Instructions) or "
+ "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
def FeatureStdExtZcf
: RISCVExtension<"zcf", 1, 0, "HasStdExtZcf", "true",
@@ -811,8 +811,8 @@ def FeatureStdExtSmaia
"'Smaia' (Advanced Interrupt Architecture Machine Level)">;
def FeatureStdExtSsaia
: RISCVExtension<"ssaia", 1, 0, "HasStdExtSsaia", "true",
- "'Ssaia' (Advanced Interrupt Architecture Supervisor "
- "Level)">;
+ "'Ssaia' (Advanced Interrupt Architecture Supervisor "
+ "Level)">;
def FeatureStdExtSmepmp
: RISCVExtension<"smepmp", 1, 0, "HasStdExtSmepmp", "true",
@@ -906,7 +906,7 @@ def FeatureStdExtSvpbmt
// present.
def FeatureStdExtSsnpm
: RISCVExperimentalExtension<"ssnpm", 0, 8, "HasStdExtSsnpm", "true",
- "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
+ "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
// A machine-level extension that provides pointer masking for the next lower
// privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
>From 4b78a1a80a6ed17601421add21f57ac3d3f3ab19 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 19 Apr 2024 15:08:37 -0700
Subject: [PATCH 3/7] fixup! Default the value to 'true'. Add documentation
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 349 +++++++++++++------------
1 file changed, 186 insertions(+), 163 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 2a28ff593402d3..d8c25cfedc3837 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -10,127 +10,148 @@
// RISC-V subtarget features and instruction predicates.
//===----------------------------------------------------------------------===//
-class RISCVExtension<string n, int major, int minor, string f, string v,
- string d, list<RISCVExtension> i = []>
- : SubtargetFeature<n, f, v, d,
- !foreach(feature, i, !cast<SubtargetFeature>(feature))> {
+// Subclass of SubtargetFeature to be used when the feature is also a RISC-V
+// extension. Extensions have a version and may be experimental.
+//
+// name - Name of the extension in lower case.q
+// major - Major version of extension
+// minor - Minor version of extension
+// fieldname - name of field to create in RISCVSubtarget.
+// desc - Description of extension
+// implies - Extensions or features implied by this extension.
+// value - Value to assign to the field in RISCVSubtarget when this
+// extension is enabled. Usually "true".
+class RISCVExtension<string name, int major, int minor, string fieldname,
+ string desc, list<SubtargetFeature> implies = [],
+ string value = "true">
+ : SubtargetFeature<name, fieldname, value, desc, implies> {
+ // MajorVersion - The major version for this extension.
int MajorVersion = major;
+
+ // MajorVersion - The minor version for this extension.
int MinorVersion = minor;
+
+ // Experimental - Does this extension require -menable-experimental-extensions
bit Experimental = false;
}
-class RISCVExperimentalExtension<string n, int major, int minor, string f,
- string v, string d, list<RISCVExtension> i = []>
- : RISCVExtension<"experimental-"#n, major, minor, f, v, d, i> {
+// Version of RISCVExtension to be used for Experimental extensions. This
+// sets the Experimental flag and prepends experimental- to the -mattr name.
+class RISCVExperimentalExtension<string name, int major, int minor,
+ string fieldname, string desc,
+ list<RISCVExtension> implies = [],
+ string value = "true">
+ : RISCVExtension<"experimental-"#name, major, minor, fieldname, desc, implies,
+ value> {
let Experimental = true;
}
// Integer Extensions
def FeatureStdExtI
- : RISCVExtension<"i", 2, 1, "HasStdExtI", "true",
+ : RISCVExtension<"i", 2, 1, "HasStdExtI",
"'I' (Base Integer Instruction Set)">;
def FeatureStdExtZic64b
- : RISCVExtension<"zic64b", 1, 0, "HasStdExtZic64b", "true",
+ : RISCVExtension<"zic64b", 1, 0, "HasStdExtZic64b",
"'Zic64b' (Cache Block Size Is 64 Bytes)">;
def FeatureStdExtZicbom
- : RISCVExtension<"zicbom", 1, 0, "HasStdExtZicbom", "true",
+ : RISCVExtension<"zicbom", 1, 0, "HasStdExtZicbom",
"'Zicbom' (Cache-Block Management Instructions)">;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
def FeatureStdExtZicbop
- : RISCVExtension<"zicbop", 1, 0, "HasStdExtZicbop", "true",
+ : RISCVExtension<"zicbop", 1, 0, "HasStdExtZicbop",
"'Zicbop' (Cache-Block Prefetch Instructions)">;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
def FeatureStdExtZicboz
- : RISCVExtension<"zicboz", 1, 0, "HasStdExtZicboz", "true",
+ : RISCVExtension<"zicboz", 1, 0, "HasStdExtZicboz",
"'Zicboz' (Cache-Block Zero Instructions)">;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
def FeatureStdExtZiccamoa
- : RISCVExtension<"ziccamoa", 1, 0, "HasStdExtZiccamoa", "true",
+ : RISCVExtension<"ziccamoa", 1, 0, "HasStdExtZiccamoa",
"'Ziccamoa' (Main Memory Supports All Atomics in A)">;
def FeatureStdExtZiccif
- : RISCVExtension<"ziccif", 1, 0, "HasStdExtZiccif", "true",
+ : RISCVExtension<"ziccif", 1, 0, "HasStdExtZiccif",
"'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
def FeatureStdExtZicclsm
- : RISCVExtension<"zicclsm", 1, 0, "HasStdExtZicclsm", "true",
+ : RISCVExtension<"zicclsm", 1, 0, "HasStdExtZicclsm",
"'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
def FeatureStdExtZiccrse
- : RISCVExtension<"ziccrse", 1, 0, "HasStdExtZiccrse", "true",
+ : RISCVExtension<"ziccrse", 1, 0, "HasStdExtZiccrse",
"'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
def FeatureStdExtZicsr
- : RISCVExtension<"zicsr", 2, 0, "HasStdExtZicsr", "true",
+ : RISCVExtension<"zicsr", 2, 0, "HasStdExtZicsr",
"'zicsr' (CSRs)">;
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
def FeatureStdExtZicntr
- : RISCVExtension<"zicntr", 2, 0, "HasStdExtZicntr", "true",
+ : RISCVExtension<"zicntr", 2, 0, "HasStdExtZicntr",
"'Zicntr' (Base Counters and Timers)",
[FeatureStdExtZicsr]>;
def FeatureStdExtZicond
- : RISCVExtension<"zicond", 1, 0, "HasStdExtZicond", "true",
+ : RISCVExtension<"zicond", 1, 0, "HasStdExtZicond",
"'Zicond' (Integer Conditional Operations)">;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
def FeatureStdExtZifencei
- : RISCVExtension<"zifencei", 2, 0, "HasStdExtZifencei", "true",
+ : RISCVExtension<"zifencei", 2, 0, "HasStdExtZifencei",
"'Zifencei' (fence.i)">;
def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
def FeatureStdExtZihintpause
- : RISCVExtension<"zihintpause", 2, 0, "HasStdExtZihintpause", "true",
+ : RISCVExtension<"zihintpause", 2, 0, "HasStdExtZihintpause",
"'Zihintpause' (Pause Hint)">;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
def FeatureStdExtZihintntl
- : RISCVExtension<"zihintntl", 1, 0, "HasStdExtZihintntl", "true",
+ : RISCVExtension<"zihintntl", 1, 0, "HasStdExtZihintntl",
"'Zihintntl' (Non-Temporal Locality Hints)">;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
def FeatureStdExtZihpm
- : RISCVExtension<"zihpm", 2, 0, "HasStdExtZihpm", "true",
+ : RISCVExtension<"zihpm", 2, 0, "HasStdExtZihpm",
"'Zihpm' (Hardware Performance Counters)",
[FeatureStdExtZicsr]>;
-def FeatureStdExtZimop : RISCVExtension<"zimop", 1, 0, "HasStdExtZimop", "true",
+def FeatureStdExtZimop : RISCVExtension<"zimop", 1, 0, "HasStdExtZimop",
"'Zimop' (May-Be-Operations)">;
def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
def FeatureStdExtZicfilp
- : RISCVExperimentalExtension<"zicfilp", 0, 4, "HasStdExtZicfilp", "true",
+ : RISCVExperimentalExtension<"zicfilp", 0, 4, "HasStdExtZicfilp",
"'Zicfilp' (Landing pad)">;
def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
AssemblerPredicate<(all_of FeatureStdExtZicfilp),
"'Zicfilp' (Landing pad)">;
def FeatureStdExtZicfiss
- : RISCVExperimentalExtension<"zicfiss", 0, 4, "HasStdExtZicfiss", "true",
+ : RISCVExperimentalExtension<"zicfiss", 0, 4, "HasStdExtZicfiss",
"'Zicfiss' (Shadow stack)",
[FeatureStdExtZicsr, FeatureStdExtZimop]>;
def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
@@ -141,14 +162,14 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
// Multiply Extensions
def FeatureStdExtM
- : RISCVExtension<"m", 2, 0, "HasStdExtM", "true",
+ : RISCVExtension<"m", 2, 0, "HasStdExtM",
"'M' (Integer Multiplication and Division)">;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
def FeatureStdExtZmmul
- : RISCVExtension<"zmmul", 1, 0, "HasStdExtZmmul", "true",
+ : RISCVExtension<"zmmul", 1, 0, "HasStdExtZmmul",
"'Zmmul' (Integer Multiplication)">;
def HasStdExtMOrZmmul
@@ -160,28 +181,28 @@ def HasStdExtMOrZmmul
// Atomic Extensions
def FeatureStdExtA
- : RISCVExtension<"a", 2, 1, "HasStdExtA", "true",
+ : RISCVExtension<"a", 2, 1, "HasStdExtA",
"'A' (Atomic Instructions)">;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
def FeatureStdExtZtso
- : RISCVExperimentalExtension<"ztso", 0, 1, "HasStdExtZtso", "true",
+ : RISCVExperimentalExtension<"ztso", 0, 1, "HasStdExtZtso",
"'Ztso' (Memory Model - Total Store Order)">;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
-def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0, "HasStdExtZa64rs", "true",
+def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0, "HasStdExtZa64rs",
"'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
-def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0, "HasStdExtZa128rs", "true",
+def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0, "HasStdExtZa128rs",
"'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
def FeatureStdExtZaamo
- : RISCVExperimentalExtension<"zaamo", 0, 2, "HasStdExtZaamo", "true",
+ : RISCVExperimentalExtension<"zaamo", 0, 2, "HasStdExtZaamo",
"'Zaamo' (Atomic Memory Operations)">;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
@@ -190,14 +211,14 @@ def HasStdExtAOrZaamo
"'Zaamo' (Atomic Memory Operations)">;
def FeatureStdExtZabha
- : RISCVExperimentalExtension<"zabha", 1, 0, "HasStdExtZabha", "true",
+ : RISCVExperimentalExtension<"zabha", 1, 0, "HasStdExtZabha",
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
AssemblerPredicate<(all_of FeatureStdExtZabha),
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
def FeatureStdExtZacas
- : RISCVExtension<"zacas", 1, 0, "HasStdExtZacas", "true",
+ : RISCVExtension<"zacas", 1, 0, "HasStdExtZacas",
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
AssemblerPredicate<(all_of FeatureStdExtZacas),
@@ -205,14 +226,14 @@ def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
def FeatureStdExtZalasr
- : RISCVExperimentalExtension<"zalasr", 0, 1, "HasStdExtZalasr", "true",
+ : RISCVExperimentalExtension<"zalasr", 0, 1, "HasStdExtZalasr",
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
AssemblerPredicate<(all_of FeatureStdExtZalasr),
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
def FeatureStdExtZalrsc
- : RISCVExperimentalExtension<"zalrsc", 0, 2, "HasStdExtZalrsc", "true",
+ : RISCVExperimentalExtension<"zalrsc", 0, 2, "HasStdExtZalrsc",
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
@@ -221,10 +242,10 @@ def HasStdExtAOrZalrsc
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
def FeatureStdExtZama16b
- : RISCVExtension<"zama16b", 1, 0, "HasStdExtZama16b", "true",
+ : RISCVExtension<"zama16b", 1, 0, "HasStdExtZama16b",
"'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
-def FeatureStdExtZawrs : RISCVExtension<"zawrs", 1, 0, "HasStdExtZawrs", "true",
+def FeatureStdExtZawrs : RISCVExtension<"zawrs", 1, 0, "HasStdExtZawrs",
"'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
AssemblerPredicate<(all_of FeatureStdExtZawrs),
@@ -233,7 +254,7 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
// Floating Point Extensions
def FeatureStdExtF
- : RISCVExtension<"f", 2, 2, "HasStdExtF", "true",
+ : RISCVExtension<"f", 2, 2, "HasStdExtF",
"'F' (Single-Precision Floating-Point)",
[FeatureStdExtZicsr]>;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
@@ -241,7 +262,7 @@ def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
"'F' (Single-Precision Floating-Point)">;
def FeatureStdExtD
- : RISCVExtension<"d", 2, 2, "HasStdExtD", "true",
+ : RISCVExtension<"d", 2, 2, "HasStdExtD",
"'D' (Double-Precision Floating-Point)",
[FeatureStdExtF]>;
def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
@@ -249,7 +270,7 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
"'D' (Double-Precision Floating-Point)">;
def FeatureStdExtZfhmin
- : RISCVExtension<"zfhmin", 1, 0, "HasStdExtZfhmin", "true",
+ : RISCVExtension<"zfhmin", 1, 0, "HasStdExtZfhmin",
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
[FeatureStdExtF]>;
def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
@@ -258,7 +279,7 @@ def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
"'Zfhmin' (Half-Precision Floating-Point Minimal)">;
def FeatureStdExtZfh
- : RISCVExtension<"zfh", 1, 0, "HasStdExtZfh", "true",
+ : RISCVExtension<"zfh", 1, 0, "HasStdExtZfh",
"'Zfh' (Half-Precision Floating-Point)",
[FeatureStdExtZfhmin]>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
@@ -267,7 +288,7 @@ def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
def FeatureStdExtZfbfmin
- : RISCVExperimentalExtension<"zfbfmin", 1, 0, "HasStdExtZfbfmin", "true",
+ : RISCVExperimentalExtension<"zfbfmin", 1, 0, "HasStdExtZfbfmin",
"'Zfbfmin' (Scalar BF16 Converts)",
[FeatureStdExtF]>;
def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
@@ -283,7 +304,7 @@ def HasHalfFPLoadStoreMove
"'Zfbfmin' (Scalar BF16 Converts)">;
def FeatureStdExtZfa
- : RISCVExtension<"zfa", 1, 0, "HasStdExtZfa", "true",
+ : RISCVExtension<"zfa", 1, 0, "HasStdExtZfa",
"'Zfa' (Additional Floating-Point)",
[FeatureStdExtF]>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
@@ -291,7 +312,7 @@ def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
"'Zfa' (Additional Floating-Point)">;
def FeatureStdExtZfinx
- : RISCVExtension<"zfinx", 1, 0, "HasStdExtZfinx", "true",
+ : RISCVExtension<"zfinx", 1, 0, "HasStdExtZfinx",
"'Zfinx' (Float in Integer)",
[FeatureStdExtZicsr]>;
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
@@ -299,7 +320,7 @@ def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
"'Zfinx' (Float in Integer)">;
def FeatureStdExtZdinx
- : RISCVExtension<"zdinx", 1, 0, "HasStdExtZdinx", "true",
+ : RISCVExtension<"zdinx", 1, 0, "HasStdExtZdinx",
"'Zdinx' (Double in Integer)",
[FeatureStdExtZfinx]>;
def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
@@ -307,7 +328,7 @@ def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
"'Zdinx' (Double in Integer)">;
def FeatureStdExtZhinxmin
- : RISCVExtension<"zhinxmin", 1, 0, "HasStdExtZhinxmin", "true",
+ : RISCVExtension<"zhinxmin", 1, 0, "HasStdExtZhinxmin",
"'Zhinxmin' (Half Float in Integer Minimal)",
[FeatureStdExtZfinx]>;
def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
@@ -316,7 +337,7 @@ def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
"'Zhinxmin' (Half Float in Integer Minimal)">;
def FeatureStdExtZhinx
- : RISCVExtension<"zhinx", 1, 0, "HasStdExtZhinx", "true",
+ : RISCVExtension<"zhinx", 1, 0, "HasStdExtZhinx",
"'Zhinx' (Half Float in Integer)",
[FeatureStdExtZhinxmin]>;
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
@@ -327,7 +348,7 @@ def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
// Compressed Extensions
def FeatureStdExtC
- : RISCVExtension<"c", 2, 0, "HasStdExtC", "true",
+ : RISCVExtension<"c", 2, 0, "HasStdExtC",
"'C' (Compressed Instructions)">;
def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
@@ -341,7 +362,7 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
"RVC Hint Instructions">;
def FeatureStdExtZca
- : RISCVExtension<"zca", 1, 0, "HasStdExtZca", "true",
+ : RISCVExtension<"zca", 1, 0, "HasStdExtZca",
"'Zca' (part of the C extension, excluding compressed "
"floating point loads/stores)">;
@@ -353,7 +374,7 @@ def HasStdExtCOrZca
"compressed floating point loads/stores)">;
def FeatureStdExtZcb
- : RISCVExtension<"zcb", 1, 0, "HasStdExtZcb", "true",
+ : RISCVExtension<"zcb", 1, 0, "HasStdExtZcb",
"'Zcb' (Compressed basic bit manipulation instructions)",
[FeatureStdExtZca]>;
def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
@@ -361,7 +382,7 @@ def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
"'Zcb' (Compressed basic bit manipulation instructions)">;
def FeatureStdExtZcd
- : RISCVExtension<"zcd", 1, 0, "HasStdExtZcd", "true",
+ : RISCVExtension<"zcd", 1, 0, "HasStdExtZcd",
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
[FeatureStdExtZca]>;
@@ -372,12 +393,12 @@ def HasStdExtCOrZcd
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
def FeatureStdExtZcf
- : RISCVExtension<"zcf", 1, 0, "HasStdExtZcf", "true",
+ : RISCVExtension<"zcf", 1, 0, "HasStdExtZcf",
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
[FeatureStdExtZca]>;
def FeatureStdExtZcmp
- : RISCVExtension<"zcmp", 1, 0, "HasStdExtZcmp", "true",
+ : RISCVExtension<"zcmp", 1, 0, "HasStdExtZcmp",
"'Zcmp' (sequenced instuctions for code-size reduction)",
[FeatureStdExtZca]>;
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
@@ -385,7 +406,7 @@ def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdE
"'Zcmp' (sequenced instuctions for code-size reduction)">;
def FeatureStdExtZcmt
- : RISCVExtension<"zcmt", 1, 0, "HasStdExtZcmt", "true",
+ : RISCVExtension<"zcmt", 1, 0, "HasStdExtZcmt",
"'Zcmt' (table jump instuctions for code-size reduction)",
[FeatureStdExtZca, FeatureStdExtZicsr]>;
def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
@@ -393,7 +414,7 @@ def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
"'Zcmt' (table jump instuctions for code-size reduction)">;
def FeatureStdExtZce
- : RISCVExtension<"zce", 1, 0, "HasStdExtZce", "true",
+ : RISCVExtension<"zce", 1, 0, "HasStdExtZce",
"'Zce' (Compressed extensions for microcontrollers)",
[FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
FeatureStdExtZcmt]>;
@@ -406,7 +427,7 @@ def HasStdExtCOrZcfOrZce
"'C' (Compressed Instructions) or "
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
-def FeatureStdExtZcmop : RISCVExtension<"zcmop", 1, 0, "HasStdExtZcmop", "true",
+def FeatureStdExtZcmop : RISCVExtension<"zcmop", 1, 0, "HasStdExtZcmop",
"'Zcmop' (Compressed May-Be-Operations)",
[FeatureStdExtZca]>;
def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
@@ -416,7 +437,7 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
// Bitmanip Extensions
def FeatureStdExtZba
- : RISCVExtension<"zba", 1, 0, "HasStdExtZba", "true",
+ : RISCVExtension<"zba", 1, 0, "HasStdExtZba",
"'Zba' (Address Generation Instructions)">;
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
AssemblerPredicate<(all_of FeatureStdExtZba),
@@ -424,21 +445,21 @@ def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
def FeatureStdExtZbb
- : RISCVExtension<"zbb", 1, 0, "HasStdExtZbb", "true",
+ : RISCVExtension<"zbb", 1, 0, "HasStdExtZbb",
"'Zbb' (Basic Bit-Manipulation)">;
def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
AssemblerPredicate<(all_of FeatureStdExtZbb),
"'Zbb' (Basic Bit-Manipulation)">;
def FeatureStdExtZbc
- : RISCVExtension<"zbc", 1, 0, "HasStdExtZbc", "true",
+ : RISCVExtension<"zbc", 1, 0, "HasStdExtZbc",
"'Zbc' (Carry-Less Multiplication)">;
def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
AssemblerPredicate<(all_of FeatureStdExtZbc),
"'Zbc' (Carry-Less Multiplication)">;
def FeatureStdExtZbs
- : RISCVExtension<"zbs", 1, 0, "HasStdExtZbs", "true",
+ : RISCVExtension<"zbs", 1, 0, "HasStdExtZbs",
"'Zbs' (Single-Bit Instructions)">;
def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
AssemblerPredicate<(all_of FeatureStdExtZbs),
@@ -447,14 +468,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
// Bitmanip Extensions for Cryptography Extensions
def FeatureStdExtZbkb
- : RISCVExtension<"zbkb", 1, 0, "HasStdExtZbkb", "true",
+ : RISCVExtension<"zbkb", 1, 0, "HasStdExtZbkb",
"'Zbkb' (Bitmanip instructions for Cryptography)">;
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
AssemblerPredicate<(all_of FeatureStdExtZbkb),
"'Zbkb' (Bitmanip instructions for Cryptography)">;
def FeatureStdExtZbkx
- : RISCVExtension<"zbkx", 1, 0, "HasStdExtZbkx", "true",
+ : RISCVExtension<"zbkx", 1, 0, "HasStdExtZbkx",
"'Zbkx' (Crossbar permutation instructions)">;
def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
AssemblerPredicate<(all_of FeatureStdExtZbkx),
@@ -470,7 +491,7 @@ def HasStdExtZbbOrZbkb
// carry-less multiply subextension. The former should be enabled if the latter
// is enabled.
def FeatureStdExtZbkc
- : RISCVExtension<"zbkc", 1, 0, "HasStdExtZbkc", "true",
+ : RISCVExtension<"zbkc", 1, 0, "HasStdExtZbkc",
"'Zbkc' (Carry-less multiply instructions for "
"Cryptography)">;
def HasStdExtZbkc
@@ -488,14 +509,14 @@ def HasStdExtZbcOrZbkc
// Cryptography Extensions
def FeatureStdExtZknd
- : RISCVExtension<"zknd", 1, 0, "HasStdExtZknd", "true",
+ : RISCVExtension<"zknd", 1, 0, "HasStdExtZknd",
"'Zknd' (NIST Suite: AES Decryption)">;
def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
AssemblerPredicate<(all_of FeatureStdExtZknd),
"'Zknd' (NIST Suite: AES Decryption)">;
def FeatureStdExtZkne
- : RISCVExtension<"zkne", 1, 0, "HasStdExtZkne", "true",
+ : RISCVExtension<"zkne", 1, 0, "HasStdExtZkne",
"'Zkne' (NIST Suite: AES Encryption)">;
def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
AssemblerPredicate<(all_of FeatureStdExtZkne),
@@ -510,35 +531,35 @@ def HasStdExtZkndOrZkne
"'Zkne' (NIST Suite: AES Encryption)">;
def FeatureStdExtZknh
- : RISCVExtension<"zknh", 1, 0, "HasStdExtZknh", "true",
+ : RISCVExtension<"zknh", 1, 0, "HasStdExtZknh",
"'Zknh' (NIST Suite: Hash Function Instructions)">;
def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
AssemblerPredicate<(all_of FeatureStdExtZknh),
"'Zknh' (NIST Suite: Hash Function Instructions)">;
def FeatureStdExtZksed
- : RISCVExtension<"zksed", 1, 0, "HasStdExtZksed", "true",
+ : RISCVExtension<"zksed", 1, 0, "HasStdExtZksed",
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
AssemblerPredicate<(all_of FeatureStdExtZksed),
"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
def FeatureStdExtZksh
- : RISCVExtension<"zksh", 1, 0, "HasStdExtZksh", "true",
+ : RISCVExtension<"zksh", 1, 0, "HasStdExtZksh",
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
AssemblerPredicate<(all_of FeatureStdExtZksh),
"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
def FeatureStdExtZkr
- : RISCVExtension<"zkr", 1, 0, "HasStdExtZkr", "true",
+ : RISCVExtension<"zkr", 1, 0, "HasStdExtZkr",
"'Zkr' (Entropy Source Extension)">;
def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
AssemblerPredicate<(all_of FeatureStdExtZkr),
"'Zkr' (Entropy Source Extension)">;
def FeatureStdExtZkn
- : RISCVExtension<"zkn", 1, 0, "HasStdExtZkn", "true",
+ : RISCVExtension<"zkn", 1, 0, "HasStdExtZkn",
"'Zkn' (NIST Algorithm Suite)",
[FeatureStdExtZbkb,
FeatureStdExtZbkc,
@@ -548,7 +569,7 @@ def FeatureStdExtZkn
FeatureStdExtZknh]>;
def FeatureStdExtZks
- : RISCVExtension<"zks", 1, 0, "HasStdExtZks", "true",
+ : RISCVExtension<"zks", 1, 0, "HasStdExtZks",
"'Zks' (ShangMi Algorithm Suite)",
[FeatureStdExtZbkb,
FeatureStdExtZbkc,
@@ -557,11 +578,11 @@ def FeatureStdExtZks
FeatureStdExtZksh]>;
def FeatureStdExtZkt
- : RISCVExtension<"zkt", 1, 0, "HasStdExtZkt", "true",
+ : RISCVExtension<"zkt", 1, 0, "HasStdExtZkt",
"'Zkt' (Data Independent Execution Latency)">;
def FeatureStdExtZk
- : RISCVExtension<"zk", 1, 0, "HasStdExtZk", "true",
+ : RISCVExtension<"zk", 1, 0, "HasStdExtZk",
"'Zk' (Standard scalar cryptography extension)",
[FeatureStdExtZkn,
FeatureStdExtZkr,
@@ -569,54 +590,56 @@ def FeatureStdExtZk
// Vector Extensions
-def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0, "ZvlLen", "32",
- "'Zvl' (Minimum Vector Length) 32">;
+def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0, "ZvlLen",
+ "'Zvl' (Minimum Vector Length) 32", [],
+ "32">;
foreach i = { 6-16 } in {
defvar I = !shl(1, i);
def FeatureStdExtZvl#I#b :
- RISCVExtension<"zvl"#I#"b", 1, 0, "ZvlLen", !cast<string>(I),
+ RISCVExtension<"zvl"#I#"b", 1, 0, "ZvlLen",
"'Zvl' (Minimum Vector Length) "#I,
- [!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
+ [!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],
+ !cast<string>(I)>;
}
def FeatureStdExtZve32x
- : RISCVExtension<"zve32x", 1, 0, "HasStdExtZve32x", "true",
+ : RISCVExtension<"zve32x", 1, 0, "HasStdExtZve32x",
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
[FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
def FeatureStdExtZve32f
- : RISCVExtension<"zve32f", 1, 0, "HasStdExtZve32f", "true",
+ : RISCVExtension<"zve32f", 1, 0, "HasStdExtZve32f",
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
[FeatureStdExtZve32x, FeatureStdExtF]>;
def FeatureStdExtZve64x
- : RISCVExtension<"zve64x", 1, 0, "HasStdExtZve64x", "true",
+ : RISCVExtension<"zve64x", 1, 0, "HasStdExtZve64x",
"'Zve64x' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW)",
[FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
def FeatureStdExtZve64f
- : RISCVExtension<"zve64f", 1, 0, "HasStdExtZve64f", "true",
+ : RISCVExtension<"zve64f", 1, 0, "HasStdExtZve64f",
"'Zve64f' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW and F extension)",
[FeatureStdExtZve32f, FeatureStdExtZve64x]>;
def FeatureStdExtZve64d
- : RISCVExtension<"zve64d", 1, 0, "HasStdExtZve64d", "true",
+ : RISCVExtension<"zve64d", 1, 0, "HasStdExtZve64d",
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
[FeatureStdExtZve64f, FeatureStdExtD]>;
def FeatureStdExtV
- : RISCVExtension<"v", 1, 0, "HasStdExtV", "true",
+ : RISCVExtension<"v", 1, 0, "HasStdExtV",
"'V' (Vector Extension for Application Processors)",
[FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
def FeatureStdExtZvfbfmin
- : RISCVExperimentalExtension<"zvfbfmin", 1, 0, "HasStdExtZvfbfmin", "true",
+ : RISCVExperimentalExtension<"zvfbfmin", 1, 0, "HasStdExtZvfbfmin",
"'Zvbfmin' (Vector BF16 Converts)",
[FeatureStdExtZve32f]>;
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
@@ -624,7 +647,7 @@ def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
"'Zvfbfmin' (Vector BF16 Converts)">;
def FeatureStdExtZvfbfwma
- : RISCVExperimentalExtension<"zvfbfwma", 1, 0, "HasStdExtZvfbfwma", "true",
+ : RISCVExperimentalExtension<"zvfbfwma", 1, 0, "HasStdExtZvfbfwma",
"'Zvfbfwma' (Vector BF16 widening mul-add)",
[FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
@@ -632,12 +655,12 @@ def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
def FeatureStdExtZvfhmin
- : RISCVExtension<"zvfhmin", 1, 0, "HasStdExtZvfhmin", "true",
+ : RISCVExtension<"zvfhmin", 1, 0, "HasStdExtZvfhmin",
"'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
[FeatureStdExtZve32f]>;
def FeatureStdExtZvfh
- : RISCVExtension<"zvfh", 1, 0, "HasStdExtZvfh", "true",
+ : RISCVExtension<"zvfh", 1, 0, "HasStdExtZvfh",
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>;
@@ -650,14 +673,14 @@ def HasStdExtZfhOrZvfh
// Vector Cryptography and Bitmanip Extensions
def FeatureStdExtZvkb
- : RISCVExtension<"zvkb", 1, 0, "HasStdExtZvkb", "true",
+ : RISCVExtension<"zvkb", 1, 0, "HasStdExtZvkb",
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
AssemblerPredicate<(all_of FeatureStdExtZvkb),
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
def FeatureStdExtZvbb
- : RISCVExtension<"zvbb", 1, 0, "HasStdExtZvbb", "true",
+ : RISCVExtension<"zvbb", 1, 0, "HasStdExtZvbb",
"'Zvbb' (Vector basic bit-manipulation instructions)",
[FeatureStdExtZvkb]>;
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
@@ -665,35 +688,35 @@ def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
"'Zvbb' (Vector basic bit-manipulation instructions)">;
def FeatureStdExtZvbc
- : RISCVExtension<"zvbc", 1, 0, "HasStdExtZvbc", "true",
+ : RISCVExtension<"zvbc", 1, 0, "HasStdExtZvbc",
"'Zvbc' (Vector Carryless Multiplication)">;
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
AssemblerPredicate<(all_of FeatureStdExtZvbc),
"'Zvbc' (Vector Carryless Multiplication)">;
def FeatureStdExtZvkg
- : RISCVExtension<"zvkg", 1, 0, "HasStdExtZvkg", "true",
+ : RISCVExtension<"zvkg", 1, 0, "HasStdExtZvkg",
"'Zvkg' (Vector GCM instructions for Cryptography)">;
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
AssemblerPredicate<(all_of FeatureStdExtZvkg),
"'Zvkg' (Vector GCM instructions for Cryptography)">;
def FeatureStdExtZvkned
- : RISCVExtension<"zvkned", 1, 0, "HasStdExtZvkned", "true",
+ : RISCVExtension<"zvkned", 1, 0, "HasStdExtZvkned",
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
AssemblerPredicate<(all_of FeatureStdExtZvkned),
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
def FeatureStdExtZvknha
- : RISCVExtension<"zvknha", 1, 0, "HasStdExtZvknha", "true",
+ : RISCVExtension<"zvknha", 1, 0, "HasStdExtZvknha",
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
def FeatureStdExtZvknhb
- : RISCVExtension<"zvknhb", 1, 0, "HasStdExtZvknhb", "true",
+ : RISCVExtension<"zvknhb", 1, 0, "HasStdExtZvknhb",
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
[FeatureStdExtZve64x]>;
def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
@@ -705,56 +728,56 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg
"'Zvknha' or 'Zvknhb' (Vector SHA-2)">;
def FeatureStdExtZvksed
- : RISCVExtension<"zvksed", 1, 0, "HasStdExtZvksed", "true",
+ : RISCVExtension<"zvksed", 1, 0, "HasStdExtZvksed",
"'Zvksed' (SM4 Block Cipher Instructions)">;
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions)">;
def FeatureStdExtZvksh
- : RISCVExtension<"zvksh", 1, 0, "HasStdExtZvksh", "true",
+ : RISCVExtension<"zvksh", 1, 0, "HasStdExtZvksh",
"'Zvksh' (SM3 Hash Function Instructions)">;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions)">;
def FeatureStdExtZvkt
- : RISCVExtension<"zvkt", 1, 0, "HasStdExtZvkt", "true",
+ : RISCVExtension<"zvkt", 1, 0, "HasStdExtZvkt",
"'Zvkt' (Vector Data-Independent Execution Latency)">;
// Zvk short-hand extensions
def FeatureStdExtZvkn
- : RISCVExtension<"zvkn", 1, 0, "HasStdExtZvkn", "true",
+ : RISCVExtension<"zvkn", 1, 0, "HasStdExtZvkn",
"'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and "
"'Zvkt')",
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvknc
- : RISCVExtension<"zvknc", 1, 0, "HasStdExtZvknc", "true",
+ : RISCVExtension<"zvknc", 1, 0, "HasStdExtZvknc",
"'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
[FeatureStdExtZvkn, FeatureStdExtZvbc]>;
def FeatureStdExtZvkng
- : RISCVExtension<"zvkng", 1, 0, "HasStdExtZvkng", "true",
+ : RISCVExtension<"zvkng", 1, 0, "HasStdExtZvkng",
"'zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
[FeatureStdExtZvkn, FeatureStdExtZvkg]>;
def FeatureStdExtZvks
- : RISCVExtension<"zvks", 1, 0, "HasStdExtZvks", "true",
+ : RISCVExtension<"zvks", 1, 0, "HasStdExtZvks",
"'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and "
"'Zvkt')",
[FeatureStdExtZvksed, FeatureStdExtZvksh,
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
def FeatureStdExtZvksc
- : RISCVExtension<"zvksc", 1, 0, "HasStdExtZvksc", "true",
+ : RISCVExtension<"zvksc", 1, 0, "HasStdExtZvksc",
"'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
[FeatureStdExtZvks, FeatureStdExtZvbc]>;
def FeatureStdExtZvksg
- : RISCVExtension<"zvksg", 1, 0, "HasStdExtZvksg", "true",
+ : RISCVExtension<"zvksg", 1, 0, "HasStdExtZvksg",
"'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
[FeatureStdExtZvks, FeatureStdExtZvkg]>;
@@ -790,7 +813,7 @@ def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMul
// Hypervisor Extensions
def FeatureStdExtH
- : RISCVExtension<"h", 1, 0, "HasStdExtH", "true",
+ : RISCVExtension<"h", 1, 0, "HasStdExtH",
"'H' (Hypervisor)">;
def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
@@ -800,103 +823,103 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
// Supervisor extensions
def FeatureStdExtShgatpa
- : RISCVExtension<"shgatpa", 1, 0, "HasStdExtShgatpa", "true",
+ : RISCVExtension<"shgatpa", 1, 0, "HasStdExtShgatpa",
"'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)">;
def FeatureStdExtShvsatpa
- : RISCVExtension<"shvsatpa", 1, 0, "HasStdExtSvsatpa", "true",
+ : RISCVExtension<"shvsatpa", 1, 0, "HasStdExtSvsatpa",
"'Svsatpa' (vsatp supports all modes supported by satp)">;
def FeatureStdExtSmaia
- : RISCVExtension<"smaia", 1, 0, "HasStdExtSmaia", "true",
+ : RISCVExtension<"smaia", 1, 0, "HasStdExtSmaia",
"'Smaia' (Advanced Interrupt Architecture Machine Level)">;
def FeatureStdExtSsaia
- : RISCVExtension<"ssaia", 1, 0, "HasStdExtSsaia", "true",
+ : RISCVExtension<"ssaia", 1, 0, "HasStdExtSsaia",
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
"Level)">;
def FeatureStdExtSmepmp
- : RISCVExtension<"smepmp", 1, 0, "HasStdExtSmepmp", "true",
+ : RISCVExtension<"smepmp", 1, 0, "HasStdExtSmepmp",
"'Smepmp' (Enhanced Physical Memory Protection)">;
def FeatureStdExtSsccptr
- : RISCVExtension<"ssccptr", 1, 0, "HasStdExtSsccptr", "true",
+ : RISCVExtension<"ssccptr", 1, 0, "HasStdExtSsccptr",
"'Ssccptr' (Main memory supports page table reads)">;
def FeatureStdExtSscofpmf
- : RISCVExtension<"sscofpmf", 1, 0, "HasStdExtSscofpmf", "true",
+ : RISCVExtension<"sscofpmf", 1, 0, "HasStdExtSscofpmf",
"'Sscofpmf' (Count Overflow and Mode-Based Filtering)">;
def FeatureStdExtShcounterenw
- : RISCVExtension<"shcounterenw", 1, 0, "HasStdExtShcounterenw", "true",
+ : RISCVExtension<"shcounterenw", 1, 0, "HasStdExtShcounterenw",
"'Shcounterenw' (Support writeable hcounteren enable "
"bit for any hpmcounter that is not read-only zero)">;
def FeatureStdExtSscounterenw
- : RISCVExtension<"sscounterenw", 1, 0, "HasStdExtSscounterenw", "true",
+ : RISCVExtension<"sscounterenw", 1, 0, "HasStdExtSscounterenw",
"'Sscounterenw' (Support writeable scounteren enable "
"bit for any hpmcounter that is not read-only zero)">;
def FeatureStdExtSsstateen
- : RISCVExtension<"ssstateen", 1, 0, "HasStdExtSsstateen", "true",
+ : RISCVExtension<"ssstateen", 1, 0, "HasStdExtSsstateen",
"'Ssstateen' (Supervisor-mode view of the state-enable extension)">;
def FeatureStdExtSsstrict
- : RISCVExtension<"ssstrict", 1, 0, "HasStdExtSsstrict", "true",
+ : RISCVExtension<"ssstrict", 1, 0, "HasStdExtSsstrict",
"'Ssstrict' (No non-conforming extensions are present)">;
def FeatureStdExtSstc
- : RISCVExtension<"sstc", 1, 0, "HasStdExtSstc", "true",
+ : RISCVExtension<"sstc", 1, 0, "HasStdExtSstc",
"'Sstc' (Supervisor-mode timer interrupts)">;
def FeaturesSsqosid
- : RISCVExperimentalExtension<"ssqosid", 1, 0, "HasStdExtSsqosid", "true",
+ : RISCVExperimentalExtension<"ssqosid", 1, 0, "HasStdExtSsqosid",
"'Ssqosid' (Quality-of-Service (QoS) Identifiers)">;
def FeatureStdExtShtvala
- : RISCVExtension<"shtvala", 1, 0, "HasStdExtShtvala", "true",
+ : RISCVExtension<"shtvala", 1, 0, "HasStdExtShtvala",
"'Shtvala' (htval provides all needed values)">;
def FeatureStdExtShvstvala
- : RISCVExtension<"shvstvala", 1, 0, "HasStdExtShvstvala", "true",
+ : RISCVExtension<"shvstvala", 1, 0, "HasStdExtShvstvala",
"'Shvstvala' (vstval provides all needed values)">;
def FeatureStdExtSstvala
- : RISCVExtension<"sstvala", 1, 0, "HasStdExtSstvala", "true",
+ : RISCVExtension<"sstvala", 1, 0, "HasStdExtSstvala",
"'Sstvala' (stval provides all needed values)">;
def FeatureStdExtShvstvecd
- : RISCVExtension<"shvstvecd", 1, 0, "HasStdExtShvstvecd", "true",
+ : RISCVExtension<"shvstvecd", 1, 0, "HasStdExtShvstvecd",
"'Shvstvecd' (vstvec supports Direct mode)">;
def FeatureStdExtSstvecd
- : RISCVExtension<"sstvecd", 1, 0, "HasStdExtSstvecd", "true",
+ : RISCVExtension<"sstvecd", 1, 0, "HasStdExtSstvecd",
"'Sstvecd' (stvec supports Direct mode)">;
def FeatureStdExtSsu64xl
- : RISCVExtension<"ssu64xl", 1, 0, "HasStdExtSsu64xl", "true",
+ : RISCVExtension<"ssu64xl", 1, 0, "HasStdExtSsu64xl",
"'Ssu64xl' (UXLEN=64 supported)">;
def FeatureStdExtSvade
- : RISCVExtension<"svade", 1, 0, "HasStdExtSvade", "true",
+ : RISCVExtension<"svade", 1, 0, "HasStdExtSvade",
"'Svade' (Raise exceptions on improper A/D bits)">;
def FeatureStdExtSvadu
- : RISCVExtension<"svadu", 1, 0, "HasStdExtSvadu", "true",
+ : RISCVExtension<"svadu", 1, 0, "HasStdExtSvadu",
"'Svadu' (Hardware A/D updates)">;
def FeatureStdExtSvbare
- : RISCVExtension<"svbare", 1, 0, "HasStdExtSvbare", "true",
+ : RISCVExtension<"svbare", 1, 0, "HasStdExtSvbare",
"'Svbare' $(satp mode Bare supported)">;
def FeatureStdExtSvinval
- : RISCVExtension<"svinval", 1, 0, "HasStdExtSvinval", "true",
+ : RISCVExtension<"svinval", 1, 0, "HasStdExtSvinval",
"'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
AssemblerPredicate<(all_of FeatureStdExtSvinval),
"'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
def FeatureStdExtSvnapot
- : RISCVExtension<"svnapot", 1, 0, "HasStdExtSvnapot", "true",
+ : RISCVExtension<"svnapot", 1, 0, "HasStdExtSvnapot",
"'Svnapot' (NAPOT Translation Contiguity)">;
def FeatureStdExtSvpbmt
- : RISCVExtension<"svpbmt", 1, 0, "HasStdExtSvpbmt", "true",
+ : RISCVExtension<"svpbmt", 1, 0, "HasStdExtSvpbmt",
"'Svpbmt' (Page-Based Memory Types)">;
// Pointer Masking extensions
@@ -905,32 +928,32 @@ def FeatureStdExtSvpbmt
// privilege mode (U-mode), and for VS- and VU-modes if the H extension is
// present.
def FeatureStdExtSsnpm
- : RISCVExperimentalExtension<"ssnpm", 0, 8, "HasStdExtSsnpm", "true",
+ : RISCVExperimentalExtension<"ssnpm", 0, 8, "HasStdExtSsnpm",
"'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
// A machine-level extension that provides pointer masking for the next lower
// privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
def FeatureStdExtSmnpm
- : RISCVExperimentalExtension<"smnpm", 0, 8, "HasStdExtSmnpm", "true",
+ : RISCVExperimentalExtension<"smnpm", 0, 8, "HasStdExtSmnpm",
"'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">;
// A machine-level extension that provides pointer masking for M-mode.
def FeatureStdExtSmmpm
- : RISCVExperimentalExtension<"smmpm", 0, 8, "HasStdExtSmmpm", "true",
+ : RISCVExperimentalExtension<"smmpm", 0, 8, "HasStdExtSmmpm",
"'Smmpm' (Machine-level Pointer Masking for M-mode)">;
// An extension that indicates that there is pointer-masking support available
// in supervisor mode, with some facility provided in the supervisor execution
// environment to control pointer masking.
def FeatureStdExtSspm
- : RISCVExperimentalExtension<"sspm", 0, 8, "HasStdExtSspm", "true",
+ : RISCVExperimentalExtension<"sspm", 0, 8, "HasStdExtSspm",
"'Sspm' (Indicates Supervisor-mode Pointer Masking)">;
// An extension that indicates that there is pointer-masking support available
// in user mode, with some facility provided in the application execution
// environment to control pointer masking.
def FeatureStdExtSupm
- : RISCVExperimentalExtension<"supm", 0, 8, "HasStdExtSupm", "true",
+ : RISCVExperimentalExtension<"supm", 0, 8, "HasStdExtSupm",
"'Supm' (Indicates User-mode Pointer Masking)">;
//===----------------------------------------------------------------------===//
@@ -940,7 +963,7 @@ def FeatureStdExtSupm
// Ventana Extenions
def FeatureVendorXVentanaCondOps
- : RISCVExtension<"xventanacondops", 1, 0, "HasVendorXVentanaCondOps", "true",
+ : RISCVExtension<"xventanacondops", 1, 0, "HasVendorXVentanaCondOps",
"'XVentanaCondOps' (Ventana Conditional Ops)">;
def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
@@ -949,42 +972,42 @@ def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()"
// T-Head Extensions
def FeatureVendorXTHeadBa
- : RISCVExtension<"xtheadba", 1, 0, "HasVendorXTHeadBa", "true",
+ : RISCVExtension<"xtheadba", 1, 0, "HasVendorXTHeadBa",
"'xtheadba' (T-Head address calculation instructions)">;
def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadBa),
"'xtheadba' (T-Head address calculation instructions)">;
def FeatureVendorXTHeadBb
- : RISCVExtension<"xtheadbb", 1, 0, "HasVendorXTHeadBb", "true",
+ : RISCVExtension<"xtheadbb", 1, 0, "HasVendorXTHeadBb",
"'xtheadbb' (T-Head basic bit-manipulation instructions)">;
def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadBb),
"'xtheadbb' (T-Head basic bit-manipulation instructions)">;
def FeatureVendorXTHeadBs
- : RISCVExtension<"xtheadbs", 1, 0, "HasVendorXTHeadBs", "true",
+ : RISCVExtension<"xtheadbs", 1, 0, "HasVendorXTHeadBs",
"'xtheadbs' (T-Head single-bit instructions)">;
def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadBs),
"'xtheadbs' (T-Head single-bit instructions)">;
def FeatureVendorXTHeadCondMov
- : RISCVExtension<"xtheadcondmov", 1, 0, "HasVendorXTHeadCondMov", "true",
+ : RISCVExtension<"xtheadcondmov", 1, 0, "HasVendorXTHeadCondMov",
"'xtheadcondmov' (T-Head conditional move instructions)">;
def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov),
"'xtheadcondmov' (T-Head conditional move instructions)">;
def FeatureVendorXTHeadCmo
- : RISCVExtension<"xtheadcmo", 1, 0, "HasVendorXTHeadCmo", "true",
+ : RISCVExtension<"xtheadcmo", 1, 0, "HasVendorXTHeadCmo",
"'xtheadcmo' (T-Head cache management instructions)">;
def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadCmo),
"'xtheadcmo' (T-Head cache management instructions)">;
def FeatureVendorXTHeadFMemIdx
- : RISCVExtension<"xtheadfmemidx", 1, 0, "HasVendorXTHeadFMemIdx", "true",
+ : RISCVExtension<"xtheadfmemidx", 1, 0, "HasVendorXTHeadFMemIdx",
"'xtheadfmemidx' (T-Head FP Indexed Memory Operations)",
[FeatureStdExtF]>;
def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">,
@@ -992,35 +1015,35 @@ def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">,
"'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">;
def FeatureVendorXTHeadMac
- : RISCVExtension<"xtheadmac", 1, 0, "HasVendorXTHeadMac", "true",
+ : RISCVExtension<"xtheadmac", 1, 0, "HasVendorXTHeadMac",
"'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadMac),
"'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
def FeatureVendorXTHeadMemIdx
- : RISCVExtension<"xtheadmemidx", 1, 0, "HasVendorXTHeadMemIdx", "true",
+ : RISCVExtension<"xtheadmemidx", 1, 0, "HasVendorXTHeadMemIdx",
"'xtheadmemidx' (T-Head Indexed Memory Operations)">;
def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx),
"'xtheadmemidx' (T-Head Indexed Memory Operations)">;
def FeatureVendorXTHeadMemPair
- : RISCVExtension<"xtheadmempair", 1, 0, "HasVendorXTHeadMemPair", "true",
+ : RISCVExtension<"xtheadmempair", 1, 0, "HasVendorXTHeadMemPair",
"'xtheadmempair' (T-Head two-GPR Memory Operations)">;
def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair),
"'xtheadmempair' (T-Head two-GPR Memory Operations)">;
def FeatureVendorXTHeadSync
- : RISCVExtension<"xtheadsync", 1, 0, "HasVendorXTHeadSync", "true",
+ : RISCVExtension<"xtheadsync", 1, 0, "HasVendorXTHeadSync",
"'xtheadsync' (T-Head multicore synchronization instructions)">;
def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadSync),
"'xtheadsync' (T-Head multicore synchronization instructions)">;
def FeatureVendorXTHeadVdot
- : RISCVExtension<"xtheadvdot", 1, 0, "HasVendorXTHeadVdot", "true",
+ : RISCVExtension<"xtheadvdot", 1, 0, "HasVendorXTHeadVdot",
"'xtheadvdot' (T-Head Vector Extensions for Dot)",
[FeatureStdExtV]>;
def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
@@ -1030,7 +1053,7 @@ def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
// SiFive Extensions
def FeatureVendorXSfvcp
- : RISCVExtension<"xsfvcp", 1, 0, "HasVendorXSfvcp", "true",
+ : RISCVExtension<"xsfvcp", 1, 0, "HasVendorXSfvcp",
"'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
[FeatureStdExtZve32x]>;
def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
@@ -1038,7 +1061,7 @@ def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
"'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">;
def FeatureVendorXSfvqmaccdod
- : RISCVExtension<"xsfvqmaccdod", 1, 0, "HasVendorXSfvqmaccdod", "true",
+ : RISCVExtension<"xsfvqmaccdod", 1, 0, "HasVendorXSfvqmaccdod",
"'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
[FeatureStdExtZve32x]>;
def HasVendorXSfvqmaccdod
@@ -1047,7 +1070,7 @@ def HasVendorXSfvqmaccdod
"'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))">;
def FeatureVendorXSfvqmaccqoq
- : RISCVExtension<"xsfvqmaccqoq", 1, 0, "HasVendorXSfvqmaccqoq", "true",
+ : RISCVExtension<"xsfvqmaccqoq", 1, 0, "HasVendorXSfvqmaccqoq",
"'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",
[FeatureStdExtZve32x]>;
def HasVendorXSfvqmaccqoq
@@ -1056,7 +1079,7 @@ def HasVendorXSfvqmaccqoq
"'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))">;
def FeatureVendorXSfvfwmaccqqq
- : RISCVExtension<"xsfvfwmaccqqq", 1, 0, "HasVendorXSfvfwmaccqqq", "true",
+ : RISCVExtension<"xsfvfwmaccqqq", 1, 0, "HasVendorXSfvfwmaccqqq",
"'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))",
[FeatureStdExtZve32f, FeatureStdExtZvfbfmin]>;
def HasVendorXSfvfwmaccqqq
@@ -1065,7 +1088,7 @@ def HasVendorXSfvfwmaccqqq
"'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))">;
def FeatureVendorXSfvfnrclipxfqf
- : RISCVExtension<"xsfvfnrclipxfqf", 1, 0, "HasVendorXSfvfnrclipxfqf", "true",
+ : RISCVExtension<"xsfvfnrclipxfqf", 1, 0, "HasVendorXSfvfnrclipxfqf",
"'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",
[FeatureStdExtZve32f]>;
def HasVendorXSfvfnrclipxfqf
@@ -1074,7 +1097,7 @@ def HasVendorXSfvfnrclipxfqf
"'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
def FeatureVendorXSiFivecdiscarddlone
- : RISCVExtension<"xsifivecdiscarddlone", 1, 0, "HasVendorXSiFivecdiscarddlone", "true",
+ : RISCVExtension<"xsifivecdiscarddlone", 1, 0, "HasVendorXSiFivecdiscarddlone",
"'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)", []>;
def HasVendorXSiFivecdiscarddlone
: Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">,
@@ -1082,7 +1105,7 @@ def HasVendorXSiFivecdiscarddlone
"'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)">;
def FeatureVendorXSiFivecflushdlone
- : RISCVExtension<"xsifivecflushdlone", 1, 0, "HasVendorXSiFivecflushdlone", "true",
+ : RISCVExtension<"xsifivecflushdlone", 1, 0, "HasVendorXSiFivecflushdlone",
"'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)", []>;
def HasVendorXSiFivecflushdlone
: Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">,
@@ -1090,7 +1113,7 @@ def HasVendorXSiFivecflushdlone
"'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)">;
def FeatureVendorXSfcease
- : RISCVExtension<"xsfcease", 1, 0, "HasVendorXSfcease", "true",
+ : RISCVExtension<"xsfcease", 1, 0, "HasVendorXSfcease",
"'XSfcease' (SiFive sf.cease Instruction)", []>;
def HasVendorXSfcease
: Predicate<"Subtarget->hasVendorXSfcease()">,
@@ -1100,7 +1123,7 @@ def HasVendorXSfcease
// Core-V Extensions
def FeatureVendorXCVelw
- : RISCVExtension<"xcvelw", 1, 0, "HasVendorXCVelw", "true",
+ : RISCVExtension<"xcvelw", 1, 0, "HasVendorXCVelw",
"'XCVelw' (CORE-V Event Load Word)">;
def HasVendorXCVelw
: Predicate<"Subtarget->hasVendorXCVelw()">,
@@ -1108,7 +1131,7 @@ def HasVendorXCVelw
"'XCVelw' (CORE-V Event Load Word)">;
def FeatureVendorXCVbitmanip
- : RISCVExtension<"xcvbitmanip", 1, 0, "HasVendorXCVbitmanip", "true",
+ : RISCVExtension<"xcvbitmanip", 1, 0, "HasVendorXCVbitmanip",
"'XCVbitmanip' (CORE-V Bit Manipulation)">;
def HasVendorXCVbitmanip
: Predicate<"Subtarget->hasVendorXCVbitmanip()">,
@@ -1116,7 +1139,7 @@ def HasVendorXCVbitmanip
"'XCVbitmanip' (CORE-V Bit Manipulation)">;
def FeatureVendorXCVmac
- : RISCVExtension<"xcvmac", 1, 0, "HasVendorXCVmac", "true",
+ : RISCVExtension<"xcvmac", 1, 0, "HasVendorXCVmac",
"'XCVmac' (CORE-V Multiply-Accumulate)">;
def HasVendorXCVmac
: Predicate<"Subtarget->hasVendorXCVmac()">,
@@ -1124,7 +1147,7 @@ def HasVendorXCVmac
"'XCVmac' (CORE-V Multiply-Accumulate)">;
def FeatureVendorXCVmem
- : RISCVExtension<"xcvmem", 1, 0, "HasVendorXCVmem", "true",
+ : RISCVExtension<"xcvmem", 1, 0, "HasVendorXCVmem",
"'XCVmem' (CORE-V Post-incrementing Load & Store)">;
def HasVendorXCVmem
: Predicate<"Subtarget->hasVendorXCVmem()">,
@@ -1132,7 +1155,7 @@ def HasVendorXCVmem
"'XCVmem' (CORE-V Post-incrementing Load & Store)">;
def FeatureVendorXCValu
- : RISCVExtension<"xcvalu", 1, 0, "HasVendorXCValu", "true",
+ : RISCVExtension<"xcvalu", 1, 0, "HasVendorXCValu",
"'XCValu' (CORE-V ALU Operations)">;
def HasVendorXCValu
: Predicate<"Subtarget->hasVendorXCValu()">,
@@ -1140,7 +1163,7 @@ def HasVendorXCValu
"'XCValu' (CORE-V ALU Operations)">;
def FeatureVendorXCVsimd
- : RISCVExtension<"xcvsimd", 1, 0, "HasVendorXCvsimd", "true",
+ : RISCVExtension<"xcvsimd", 1, 0, "HasVendorXCvsimd",
"'XCVsimd' (CORE-V SIMD ALU)">;
def HasVendorXCVsimd
: Predicate<"Subtarget->hasVendorXCVsimd()">,
@@ -1148,7 +1171,7 @@ def HasVendorXCVsimd
"'XCVsimd' (CORE-V SIMD ALU)">;
def FeatureVendorXCVbi
- : RISCVExtension<"xcvbi", 1, 0, "HasVendorXCVbi", "true",
+ : RISCVExtension<"xcvbi", 1, 0, "HasVendorXCVbi",
"'XCVbi' (CORE-V Immediate Branching)">;
def HasVendorXCVbi
: Predicate<"Subtarget->hasVendorXCVbi()">,
>From 7341c96e6e34e3dae96f4e918aaecc9d458b029c Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 18 Apr 2024 16:47:31 -0700
Subject: [PATCH 4/7] [RISCV][TableGen] Generate RISCVTargetParser.inc from the
new RISCVExtension tblgen information.
Instead of using RISCVISAInfo's extension information, use the
extension found in tblgen after #89326.
We still need to use RISCVISAInfo code to get the sorting rules for
the ISA string.
The ISA string we generate now is not quite the same extension we
had before. No implied extensions are included in the generate string
unless they are explicitly listed in RISCVProcessors.td. This primarily
affects Zicsr being implied by F, V implying Zve*, and Zvl*b implying a
smaller Zvl*b. All of these implication should be picked up when the
string is used by the frontend.
The benefit is that we get a more manageable ISA string for humans to
deal with.
This is a step towards generating RISCVISAInfo's extension list from
tblgen.
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 43 ++++++++++---------
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index e57bc6fb507e32..95b831799fb4f6 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -17,34 +17,34 @@
using namespace llvm;
-using ISAInfoTy = llvm::Expected<std::unique_ptr<RISCVISAInfo>>;
-
// We can generate march string from target features as what has been described
// in RISC-V ISA specification (version 20191213) 'Chapter 27. ISA Extension
// Naming Conventions'.
//
// This is almost the same as RISCVFeatures::parseFeatureBits, except that we
// get feature name from feature records instead of feature bits.
-static std::string getMArch(const Record &Rec) {
- std::vector<std::string> FeatureVector;
+static void printMArch(raw_ostream &OS, const Record &Rec) {
+ std::map<std::string, std::pair<unsigned, unsigned>,
+ RISCVISAInfo::ExtensionComparator>
+ Extensions;
unsigned XLen = 32;
// Convert features to FeatureVector.
for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
StringRef FeatureName = Feature->getValueAsString("Name");
- if (llvm::RISCVISAInfo::isSupportedExtensionFeature(FeatureName))
- FeatureVector.push_back((Twine("+") + FeatureName).str());
- else if (FeatureName == "64bit")
+ if (Feature->isSubClassOf("RISCVExtension")) {
+ unsigned Major = Feature->getValueAsInt("MajorVersion");
+ unsigned Minor = Feature->getValueAsInt("MinorVersion");
+ Extensions.try_emplace(FeatureName.str(), Major, Minor);
+ } else if (FeatureName == "64bit")
XLen = 64;
}
- ISAInfoTy ISAInfo = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
- if (!ISAInfo)
- report_fatal_error("Invalid features");
+ OS << "rv" << XLen;
- // RISCVISAInfo::toString will generate a march string with all the extensions
- // we have added to it.
- return (*ISAInfo)->toString();
+ ListSeparator LS("_");
+ for (auto const &Ext : Extensions)
+ OS << LS << Ext.first << Ext.second.first << 'p' << Ext.second.second;
}
static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
@@ -54,12 +54,6 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
// Iterate on all definition records.
for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) {
- std::string MArch = Rec->getValueAsString("DefaultMarch").str();
-
- // Compute MArch from features if we don't specify it.
- if (MArch.empty())
- MArch = getMArch(*Rec);
-
bool FastScalarUnalignedAccess =
any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
@@ -75,7 +69,16 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
OS << "PROC(" << Rec->getName() << ", "
<< "{\"" << Rec->getValueAsString("Name") << "\"}, "
- << "{\"" << MArch << "\"}, " << FastUnalignedAccess << ")\n";
+ << "{\"";
+
+ StringRef MArch = Rec->getValueAsString("DefaultMarch");
+
+ // Compute MArch from features if we don't specify it.
+ if (MArch.empty())
+ printMArch(OS, *Rec);
+ else
+ OS << MArch;
+ OS << "\"}, " << FastUnalignedAccess << ")\n";
}
OS << "\n#undef PROC\n";
OS << "\n";
>From 42c020334ffe95bec732b13528e4c8971c8516d4 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 18 Apr 2024 17:10:50 -0700
Subject: [PATCH 5/7] fixup! clang-format
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 95b831799fb4f6..e5be76c34d3b1c 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -67,9 +67,8 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
bool FastUnalignedAccess =
FastScalarUnalignedAccess && FastVectorUnalignedAccess;
- OS << "PROC(" << Rec->getName() << ", "
- << "{\"" << Rec->getValueAsString("Name") << "\"}, "
- << "{\"";
+ OS << "PROC(" << Rec->getName() << ", {\"" << Rec->getValueAsString("Name")
+ << "\"}, {\"";
StringRef MArch = Rec->getValueAsString("DefaultMarch");
>From 52b4ca767e8ca593a7ff37f99e15f69e6454f770 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 19 Apr 2024 15:17:27 -0700
Subject: [PATCH 6/7] fixup! Infer 32-bit Xlen from '32bit' feature.
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index e5be76c34d3b1c..9db55aa15efbf8 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -27,7 +27,7 @@ static void printMArch(raw_ostream &OS, const Record &Rec) {
std::map<std::string, std::pair<unsigned, unsigned>,
RISCVISAInfo::ExtensionComparator>
Extensions;
- unsigned XLen = 32;
+ unsigned XLen = 0;
// Convert features to FeatureVector.
for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
@@ -36,10 +36,17 @@ static void printMArch(raw_ostream &OS, const Record &Rec) {
unsigned Major = Feature->getValueAsInt("MajorVersion");
unsigned Minor = Feature->getValueAsInt("MinorVersion");
Extensions.try_emplace(FeatureName.str(), Major, Minor);
- } else if (FeatureName == "64bit")
+ } else if (FeatureName == "64bit") {
+ assert(XLen == 0 && "Already determined XLen");
XLen = 64;
+ } else if (FeatureName == "32bit") {
+ assert(XLen == 0 && "Already determined XLen");
+ XLen = 32;
+ }
}
+ assert(XLen != 0 && "Unable to determine XLen");
+
OS << "rv" << XLen;
ListSeparator LS("_");
>From 09ec289c3957d468dc3f4965c3c53e059976d098 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 19 Apr 2024 16:29:03 -0700
Subject: [PATCH 7/7] fixup! Add unit test
---
llvm/test/TableGen/riscv-target-def.td | 96 ++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 llvm/test/TableGen/riscv-target-def.td
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
new file mode 100644
index 00000000000000..f2ea3c6d4686a5
--- /dev/null
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -0,0 +1,96 @@
+// RUN: llvm-tblgen -gen-riscv-target-def -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+class RISCVExtension<string name, int major, int minor, string fieldname,
+ string desc, list<SubtargetFeature> implies = [],
+ string value = "true">
+ : SubtargetFeature<name, fieldname, value, desc, implies> {
+ int MajorVersion = major;
+ int MinorVersion = minor;
+ bit Experimental = false;
+}
+
+def FeatureStdExtI
+ : RISCVExtension<"i", 2, 1, "HasStdExtI",
+ "'I' (Base Integer Instruction Set)">;
+
+def FeatureStdExtZicsr
+ : RISCVExtension<"zicsr", 2, 0, "HasStdExtZicsr",
+ "'zicsr' (CSRs)">;
+
+def FeatureStdExtZifencei
+ : RISCVExtension<"zifencei", 2, 0, "HasStdExtZifencei",
+ "'Zifencei' (fence.i)">;
+
+def Feature32Bit
+ : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
+def Feature64Bit
+ : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
+
+// Dummy feature that isn't an extension.
+def FeatureDummy
+ : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">;
+
+class RISCVProcessorModel<string n,
+ SchedMachineModel m,
+ list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = [],
+ string default_march = "">
+ : ProcessorModel<n, m, f, tunef> {
+ string DefaultMarch = default_march;
+}
+
+class RISCVTuneProcessorModel<string n,
+ SchedMachineModel m,
+ list<SubtargetFeature> tunef = [],
+ list<SubtargetFeature> f = []>
+ : ProcessorModel<n, m, f,tunef>;
+
+def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
+ NoSchedModel,
+ [Feature32Bit,
+ FeatureStdExtI]>;
+def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI]>;
+def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>;
+
+
+def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
+ NoSchedModel,
+ [Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZifencei,
+ FeatureStdExtZicsr,
+ FeatureDummy]>;
+def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZifencei,
+ FeatureStdExtZicsr,
+ FeatureDummy]>;
+def ROCKET : RISCVTuneProcessorModel<"rocket",
+ NoSchedModel>;
+
+// CHECK: #ifndef PROC
+// CHECK: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS)
+// CHECK: #endif
+
+// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0)
+// CHECK: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0)
+// CHECK: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zifencei2p0"}, 0)
+// CHECK: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zifencei2p0"}, 0)
+
+// CHECK: #undef PROC
+
+// CHECK: #ifndef TUNE_PROC
+// CHECK: #define TUNE_PROC(ENUM, NAME)
+// CHECK: #endif
+
+// CHECK: TUNE_PROC(GENERIC, "generic")
+// CHECK: TUNE_PROC(ROCKET, "rocket")
+
+// CHECK: #undef TUNE_PROC
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