[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

[Jun Wang via llvm-commits]

================
@@ -0,0 +1,569 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX9 -enable-var-scope %s
+; RUN: llc -global-isel -stop-after=irtranslator -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX11 -enable-var-scope %s
+
+define void @void_func_i1(i1 %arg0) {
+; GFX9-LABEL: name: void_func_i1
+; GFX9: bb.1 (%ir-block.0):
+; GFX9-NEXT:   liveins: $sgpr4_sgpr5
+; GFX9-NEXT: {{  $}}
+; GFX9-NEXT:    [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr4_sgpr5
+; GFX9-NEXT:    [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
----------------
jwanggit86 wrote:

@arsenm 
In order to allow `%0:_(s1) = COPY $sgpr4_sgpr5`, is it ok to change `AMDGPURegisterBankInfo::copyCost()` as follows, i.e., allowing the src of a COPY to be the SGPR reg bank? Note that there's no context available.
```diff
unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
                                           const RegisterBank &Src,
                                           TypeSize Size) const {
   // TODO: Should there be a UniformVGPRRegBank which can use readfirstlane?
   if (Dst.getID() == AMDGPU::SGPRRegBankID &&
       (isVectorRegisterBank(Src) || Src.getID() == AMDGPU::VCCRegBankID)) {
     return std::numeric_limits<unsigned>::max();
   }

   // Bool values are tricky, because the meaning is based on context. The SCC
   // and VCC banks are for the natural scalar and vector conditions produced by
   // a compare.
   //
   // Legalization doesn't know about the necessary context, so an s1 use may
   // have been a truncate from an arbitrary value, in which case a copy (lowered
   // as a compare with 0) needs to be inserted.
   if (Size == 1 &&
       (Dst.getID() == AMDGPU::SGPRRegBankID) &&
       (isVectorRegisterBank(Src) ||
-       Src.getID() == AMDGPU::SGPRRegBankID ||
        Src.getID() == AMDGPU::VCCRegBankID))
     return std::numeric_limits<unsigned>::max();

   // There is no direct copy between AGPRs.
   if (Dst.getID() == AMDGPU::AGPRRegBankID &&
       Src.getID() == AMDGPU::AGPRRegBankID)
     return 4;

   return RegisterBankInfo::copyCost(Dst, Src, Size);
 }
```

https://github.com/llvm/llvm-project/pull/72461