[llvm] f09f99e - [RISCV] Add RISCVTuneProcessorModel to 'generic' CPU. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-04-19T16:06:54-07:00
New Revision: f09f99ed329f58c79fba43abf5fc73a28a0e2055

URL: https://github.com/llvm/llvm-project/commit/f09f99ed329f58c79fba43abf5fc73a28a0e2055
DIFF: https://github.com/llvm/llvm-project/commit/f09f99ed329f58c79fba43abf5fc73a28a0e2055.diff

LOG: [RISCV] Add RISCVTuneProcessorModel to 'generic' CPU. NFC

Remove hardcode GENERIC cpu from RISCVTargetDefEmitter.cpp.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVProcessors.td
    llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index f9a557e02bfe1a..3c86036e65fa28 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -66,7 +66,7 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
                    GenericTuneInfo;
 // Support generic for compatibility with other targets. The triple will be used
 // to change to the appropriate rv32/rv64 version.
-def : ProcessorModel<"generic", NoSchedModel, []>, GenericTuneInfo;
+def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo;
 
 def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
                                       RocketModel,

diff  --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index e57bc6fb507e32..62916bd62c0119 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -82,7 +82,6 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
   OS << "#ifndef TUNE_PROC\n"
      << "#define TUNE_PROC(ENUM, NAME)\n"
      << "#endif\n\n";
-  OS << "TUNE_PROC(GENERIC, \"generic\")\n";
 
   for (const Record *Rec :
        RK.getAllDerivedDefinitions("RISCVTuneProcessorModel")) {