[llvm] [NVPTX] Fix 64 bits rotations with large shift values (PR #89399)

[Artem Belevich via llvm-commits]

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@@ -1747,8 +1747,9 @@ def ROTL64reg_sw :
             ".reg .b64 %lhs;\n\t"
             ".reg .b64 %rhs;\n\t"
             ".reg .u32 %amt2;\n\t"
-            "shl.b64 \t%lhs, $src, $amt;\n\t"
-            "sub.u32 \t%amt2, 64, $amt;\n\t"
+            "and.b32 \t%amt2, $amt, 63;\n\t"
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Artem-B wrote:

Makes me wonder if we should add lowering for `ISD::FSHR` and `ISD::FSHR` directly, instead of only handling the case of `fshl(arg, arg, N) -> rotl(a, N)`.

https://github.com/llvm/llvm-project/pull/89399