[llvm] [RISCV][TableGen] Generate RISCVTargetParser.inc from the new RISCVExtension tblgen information. (PR #89335)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 19 09:29:53 PDT 2024
================
@@ -17,34 +17,34 @@
using namespace llvm;
-using ISAInfoTy = llvm::Expected<std::unique_ptr<RISCVISAInfo>>;
-
// We can generate march string from target features as what has been described
// in RISC-V ISA specification (version 20191213) 'Chapter 27. ISA Extension
// Naming Conventions'.
//
// This is almost the same as RISCVFeatures::parseFeatureBits, except that we
// get feature name from feature records instead of feature bits.
-static std::string getMArch(const Record &Rec) {
- std::vector<std::string> FeatureVector;
+static void printMArch(raw_ostream &OS, const Record &Rec) {
+ std::map<std::string, std::pair<unsigned, unsigned>,
+ RISCVISAInfo::ExtensionComparator>
+ Extensions;
unsigned XLen = 32;
// Convert features to FeatureVector.
for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
StringRef FeatureName = Feature->getValueAsString("Name");
- if (llvm::RISCVISAInfo::isSupportedExtensionFeature(FeatureName))
- FeatureVector.push_back((Twine("+") + FeatureName).str());
- else if (FeatureName == "64bit")
+ if (Feature->isSubClassOf("RISCVExtension")) {
+ unsigned Major = Feature->getValueAsInt("MajorVersion");
+ unsigned Minor = Feature->getValueAsInt("MinorVersion");
+ Extensions.try_emplace(FeatureName.str(), Major, Minor);
+ } else if (FeatureName == "64bit")
----------------
topperc wrote:
We're looping over the Features. This is just checking for one specific feature called "64bit". That feature isn't an "extension". It doesn't stop us from processing the other features.
https://github.com/llvm/llvm-project/pull/89335
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