[llvm] [RISCV] Add extension information to RISCVFeatures.td. NFC (PR #89326)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 23:53:34 PDT 2024
================
@@ -786,139 +804,138 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
// Supervisor extensions
def FeatureStdExtShgatpa
- : SubtargetFeature<"shgatpa", "HasStdExtShgatpa", "true",
- "'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)", []>;
+ : RISCVExtension<"shgatpa", 1, 0, "HasStdExtShgatpa", "true",
+ "'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)">;
def FeatureStdExtShvsatpa
- : SubtargetFeature<"shvsatpa", "HasStdExtSvsatpa", "true",
- "'Svsatpa' (vsatp supports all modes supported by satp)", []>;
+ : RISCVExtension<"shvsatpa", 1, 0, "HasStdExtSvsatpa", "true",
+ "'Svsatpa' (vsatp supports all modes supported by satp)">;
def FeatureStdExtSmaia
- : SubtargetFeature<"smaia", "HasStdExtSmaia", "true",
- "'Smaia' (Advanced Interrupt Architecture Machine "
- "Level)", []>;
+ : RISCVExtension<"smaia", 1, 0, "HasStdExtSmaia", "true",
+ "'Smaia' (Advanced Interrupt Architecture Machine Level)">;
def FeatureStdExtSsaia
- : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
+ : RISCVExtension<"ssaia", 1, 0, "HasStdExtSsaia", "true",
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
- "Level)", []>;
+ "Level)">;
def FeatureStdExtSmepmp
- : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
- "'Smepmp' (Enhanced Physical Memory Protection)", []>;
+ : RISCVExtension<"smepmp", 1, 0, "HasStdExtSmepmp", "true",
+ "'Smepmp' (Enhanced Physical Memory Protection)">;
def FeatureStdExtSsccptr
- : SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true",
- "'Ssccptr' (Main memory supports page table reads)", []>;
+ : RISCVExtension<"ssccptr", 1, 0, "HasStdExtSsccptr", "true",
+ "'Ssccptr' (Main memory supports page table reads)">;
def FeatureStdExtSscofpmf
- : SubtargetFeature<"sscofpmf", "HasStdExtSscofpmf", "true",
- "'Sscofpmf' (Count Overflow and Mode-Based Filtering)", []>;
+ : RISCVExtension<"sscofpmf", 1, 0, "HasStdExtSscofpmf", "true",
+ "'Sscofpmf' (Count Overflow and Mode-Based Filtering)">;
def FeatureStdExtShcounterenw
- : SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true",
- "'Shcounterenw' (Support writeable hcounteren enable "
- "bit for any hpmcounter that is not read-only zero)", []>;
+ : RISCVExtension<"shcounterenw", 1, 0, "HasStdExtShcounterenw", "true",
+ "'Shcounterenw' (Support writeable hcounteren enable "
+ "bit for any hpmcounter that is not read-only zero)">;
def FeatureStdExtSscounterenw
- : SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true",
- "'Sscounterenw' (Support writeable scounteren enable "
- "bit for any hpmcounter that is not read-only zero)", []>;
+ : RISCVExtension<"sscounterenw", 1, 0, "HasStdExtSscounterenw", "true",
+ "'Sscounterenw' (Support writeable scounteren enable "
+ "bit for any hpmcounter that is not read-only zero)">;
def FeatureStdExtSsstateen
- : SubtargetFeature<"ssstateen", "HasStdExtSsstateen", "true",
- "'Ssstateen' (Supervisor-mode view of the state-enable extension)", []>;
+ : RISCVExtension<"ssstateen", 1, 0, "HasStdExtSsstateen", "true",
+ "'Ssstateen' (Supervisor-mode view of the state-enable extension)">;
def FeatureStdExtSsstrict
- : SubtargetFeature<"ssstrict", "HasStdExtSsstrict", "true",
- "'Ssstrict' (No non-conforming extensions are present)", []>;
+ : RISCVExtension<"ssstrict", 1, 0, "HasStdExtSsstrict", "true",
+ "'Ssstrict' (No non-conforming extensions are present)">;
def FeatureStdExtSstc
- : SubtargetFeature<"sstc", "HasStdExtSstc", "true",
- "'Sstc' (Supervisor-mode timer interrupts)", []>;
+ : RISCVExtension<"sstc", 1, 0, "HasStdExtSstc", "true",
+ "'Sstc' (Supervisor-mode timer interrupts)">;
def FeaturesSsqosid
- : SubtargetFeature<"experimental-ssqosid", "HasStdExtSsqosid", "true",
- "'Ssqosid' (Quality-of-Service (QoS) Identifiers)", []>;
+ : RISCVExperimentalExtension<"ssqosid", 1, 0, "HasStdExtSsqosid", "true",
+ "'Ssqosid' (Quality-of-Service (QoS) Identifiers)">;
def FeatureStdExtShtvala
- : SubtargetFeature<"shtvala", "HasStdExtShtvala", "true",
- "'Shtvala' (htval provides all needed values)", []>;
+ : RISCVExtension<"shtvala", 1, 0, "HasStdExtShtvala", "true",
+ "'Shtvala' (htval provides all needed values)">;
def FeatureStdExtShvstvala
- : SubtargetFeature<"shvstvala", "HasStdExtShvstvala", "true",
- "'Shvstvala' (vstval provides all needed values)", []>;
+ : RISCVExtension<"shvstvala", 1, 0, "HasStdExtShvstvala", "true",
+ "'Shvstvala' (vstval provides all needed values)">;
def FeatureStdExtSstvala
- : SubtargetFeature<"sstvala", "HasStdExtSstvala", "true",
- "'Sstvala' (stval provides all needed values)", []>;
+ : RISCVExtension<"sstvala", 1, 0, "HasStdExtSstvala", "true",
+ "'Sstvala' (stval provides all needed values)">;
def FeatureStdExtShvstvecd
- : SubtargetFeature<"shvstvecd", "HasStdExtShvstvecd", "true",
- "'Shvstvecd' (vstvec supports Direct mode)", []>;
+ : RISCVExtension<"shvstvecd", 1, 0, "HasStdExtShvstvecd", "true",
+ "'Shvstvecd' (vstvec supports Direct mode)">;
def FeatureStdExtSstvecd
- : SubtargetFeature<"sstvecd", "HasStdExtSstvecd", "true",
- "'Sstvecd' (stvec supports Direct mode)", []>;
+ : RISCVExtension<"sstvecd", 1, 0, "HasStdExtSstvecd", "true",
+ "'Sstvecd' (stvec supports Direct mode)">;
def FeatureStdExtSsu64xl
- : SubtargetFeature<"ssu64xl", "HasStdExtSsu64xl", "true",
- "'Ssu64xl' (UXLEN=64 supported)", []>;
+ : RISCVExtension<"ssu64xl", 1, 0, "HasStdExtSsu64xl", "true",
+ "'Ssu64xl' (UXLEN=64 supported)">;
def FeatureStdExtSvade
- : SubtargetFeature<"svade", "HasStdExtSvade", "true",
- "'Svade' (Raise exceptions on improper A/D bits)", []>;
+ : RISCVExtension<"svade", 1, 0, "HasStdExtSvade", "true",
+ "'Svade' (Raise exceptions on improper A/D bits)">;
def FeatureStdExtSvadu
- : SubtargetFeature<"svadu", "HasStdExtSvadu", "true",
- "'Svadu' (Hardware A/D updates)", []>;
+ : RISCVExtension<"svadu", 1, 0, "HasStdExtSvadu", "true",
+ "'Svadu' (Hardware A/D updates)">;
def FeatureStdExtSvbare
- : SubtargetFeature<"svbare", "HasStdExtSvbare", "true",
- "'Svbare' $(satp mode Bare supported)", []>;
+ : RISCVExtension<"svbare", 1, 0, "HasStdExtSvbare", "true",
+ "'Svbare' $(satp mode Bare supported)">;
def FeatureStdExtSvinval
- : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
- "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
+ : RISCVExtension<"svinval", 1, 0, "HasStdExtSvinval", "true",
+ "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
AssemblerPredicate<(all_of FeatureStdExtSvinval),
"'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
def FeatureStdExtSvnapot
- : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
- "'Svnapot' (NAPOT Translation Contiguity)">;
+ : RISCVExtension<"svnapot", 1, 0, "HasStdExtSvnapot", "true",
+ "'Svnapot' (NAPOT Translation Contiguity)">;
def FeatureStdExtSvpbmt
- : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
- "'Svpbmt' (Page-Based Memory Types)">;
+ : RISCVExtension<"svpbmt", 1, 0, "HasStdExtSvpbmt", "true",
+ "'Svpbmt' (Page-Based Memory Types)">;
// Pointer Masking extensions
// A supervisor-level extension that provides pointer masking for the next lower
// privilege mode (U-mode), and for VS- and VU-modes if the H extension is
// present.
def FeatureStdExtSsnpm
- : SubtargetFeature<"experimental-ssnpm", "HasStdExtSsnpm", "true",
- "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
+ : RISCVExperimentalExtension<"ssnpm", 0, 8, "HasStdExtSsnpm", "true",
+ "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
----------------
wangpc-pp wrote:
ditto.
https://github.com/llvm/llvm-project/pull/89326
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