[llvm] [RISCV] Add extension information to RISCVFeatures.td. NFC (PR #89326)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 23:53:34 PDT 2024
================
@@ -10,115 +10,133 @@
// RISC-V subtarget features and instruction predicates.
//===----------------------------------------------------------------------===//
+class RISCVExtension<string name, int major, int minor, string fieldname,
+ string value, string desc,
+ list<RISCVExtension> implies = []>
+ : SubtargetFeature<name, fieldname, value, desc,
+ !foreach(feature, implies,
+ !cast<SubtargetFeature>(feature))> {
+ int MajorVersion = major;
+ int MinorVersion = minor;
+ bit Experimental = false;
+}
+
+class RISCVExperimentalExtension<string name, int major, int minor,
+ string fieldname, string value, string desc,
+ list<RISCVExtension> implies = []>
+ : RISCVExtension<"experimental-"#name, major, minor, fieldname, value, desc,
+ implies> {
+ let Experimental = true;
+}
+
// Integer Extensions
def FeatureStdExtI
- : SubtargetFeature<"i", "HasStdExtI", "true",
- "'I' (Base Integer Instruction Set)">;
-
+ : RISCVExtension<"i", 2, 1, "HasStdExtI", "true",
+ "'I' (Base Integer Instruction Set)">;
def FeatureStdExtZic64b
- : SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
- "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+ : RISCVExtension<"zic64b", 1, 0, "HasStdExtZic64b", "true",
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
def FeatureStdExtZicbom
- : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
- "'Zicbom' (Cache-Block Management Instructions)">;
+ : RISCVExtension<"zicbom", 1, 0, "HasStdExtZicbom", "true",
+ "'Zicbom' (Cache-Block Management Instructions)">;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
def FeatureStdExtZicbop
- : SubtargetFeature<"zicbop", "HasStdExtZicbop", "true",
- "'Zicbop' (Cache-Block Prefetch Instructions)">;
+ : RISCVExtension<"zicbop", 1, 0, "HasStdExtZicbop", "true",
+ "'Zicbop' (Cache-Block Prefetch Instructions)">;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
def FeatureStdExtZicboz
- : SubtargetFeature<"zicboz", "HasStdExtZicboz", "true",
- "'Zicboz' (Cache-Block Zero Instructions)">;
+ : RISCVExtension<"zicboz", 1, 0, "HasStdExtZicboz", "true",
+ "'Zicboz' (Cache-Block Zero Instructions)">;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
def FeatureStdExtZiccamoa
- : SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
- "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+ : RISCVExtension<"ziccamoa", 1, 0, "HasStdExtZiccamoa", "true",
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
def FeatureStdExtZiccif
- : SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
- "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
+ : RISCVExtension<"ziccif", 1, 0, "HasStdExtZiccif", "true",
+ "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
def FeatureStdExtZicclsm
- : SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
- "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
+ : RISCVExtension<"zicclsm", 1, 0, "HasStdExtZicclsm", "true",
+ "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
def FeatureStdExtZiccrse
- : SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
- "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
+ : RISCVExtension<"ziccrse", 1, 0, "HasStdExtZiccrse", "true",
+ "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
def FeatureStdExtZicsr
- : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
- "'zicsr' (CSRs)">;
+ : RISCVExtension<"zicsr", 2, 0, "HasStdExtZicsr", "true",
+ "'zicsr' (CSRs)">;
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
def FeatureStdExtZicntr
- : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
- "'Zicntr' (Base Counters and Timers)",
+ : RISCVExtension<"zicntr", 2, 0, "HasStdExtZicntr", "true",
+ "'Zicntr' (Base Counters and Timers)",
[FeatureStdExtZicsr]>;
def FeatureStdExtZicond
- : SubtargetFeature<"zicond", "HasStdExtZicond", "true",
- "'Zicond' (Integer Conditional Operations)">;
+ : RISCVExtension<"zicond", 1, 0, "HasStdExtZicond", "true",
+ "'Zicond' (Integer Conditional Operations)">;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
def FeatureStdExtZifencei
- : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
- "'Zifencei' (fence.i)">;
+ : RISCVExtension<"zifencei", 2, 0, "HasStdExtZifencei", "true",
+ "'Zifencei' (fence.i)">;
def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
def FeatureStdExtZihintpause
- : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
- "'Zihintpause' (Pause Hint)">;
+ : RISCVExtension<"zihintpause", 2, 0, "HasStdExtZihintpause", "true",
+ "'Zihintpause' (Pause Hint)">;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
def FeatureStdExtZihintntl
- : SubtargetFeature<"zihintntl", "HasStdExtZihintntl", "true",
+ : RISCVExtension<"zihintntl", 1, 0, "HasStdExtZihintntl", "true",
"'Zihintntl' (Non-Temporal Locality Hints)">;
----------------
wangpc-pp wrote:
wrong indent here.
https://github.com/llvm/llvm-project/pull/89326
More information about the llvm-commits
mailing list