[llvm] [RISCV] Implement Intrinsics Support for XCValu Extension in CV32E40P (PR #85603)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 18:06:54 PDT 2024
================
@@ -704,3 +749,51 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32] in {
(CV_BITREV GPR:$rs1, cv_tuimm2:$radix, cv_tuimm5:$pts)>;
def : Pat<(bitreverse (XLenVT GPR:$rs)), (CV_BITREV GPR:$rs, 0, 0)>;
}
+
+class PatCoreVAluGpr <string intr, string asm> :
+ PatGpr<!cast<Intrinsic>("int_riscv_cv_alu_" # intr),
+ !cast<RVInst>("CV_" # asm)>;
+class PatCoreVAluGprGpr <string intr, string asm> :
+ PatGprGpr<!cast<Intrinsic>("int_riscv_cv_alu_" # intr),
+ !cast<RVInst>("CV_" # asm)>;
+
+multiclass PatCoreVAluGprImm <Intrinsic intr> {
+ def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;
+ def : Pat<(intr (XLenVT GPR:$rs1), powerOf2Minus1:$upperBound),
+ (!cast<RVInst>("CV_" # NAME) GPR:$rs1,
+ (trailing1sPlus1 imm:$upperBound))>;
+}
+
+multiclass PatCoreVAluGprGprImm <Intrinsic intr> {
+ def : Pat<(intr GPR:$rs1, GPR:$rs2, GPR:$rs3),
+ (!cast<RVInst>("CV_" # NAME # "R") GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+ def : Pat<(intr GPR:$rs1, GPR:$rs2, uimm5:$imm),
+ (!cast<RVInst>("CV_" # NAME) GPR:$rs1, GPR:$rs2, uimm5:$imm)>;
+}
+
+let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {
+ def : PatGpr<abs, CV_ABS>;
+ def : PatGprGpr<setle, CV_SLET>;
+ def : PatGprGpr<setule, CV_SLETU>;
+ def : PatGprGpr<smin, CV_MIN>;
+ def : PatGprGpr<umin, CV_MINU>;
+ def : PatGprGpr<smax, CV_MAX>;
+ def : PatGprGpr<umax, CV_MAXU>;
+
+ def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (CV_EXTHS GPR:$rs1)>;
+ def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (CV_EXTBS GPR:$rs1)>;
+
+ def : Pat<(and (XLenVT GPR:$rs1), 0xffff), (CV_EXTHZ GPR:$rs1)>;
+ def : Pat<(and (XLenVT GPR:$rs1), 0xff), (CV_EXTBZ GPR:$rs1)>;
----------------
topperc wrote:
Why did you remove `def : Pat<(and (XLenVT GPR:$rs1), 0xffff), (CV_EXTHZ GPR:$rs1)>;`? That still seems like a useful pattern. My original question was just about CV_EXTBZ.
https://github.com/llvm/llvm-project/pull/85603
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