[llvm] [AMDGPU] Create AMDGPUMnemonicAlias tablegen class (PR #89288)
Joe Nash via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 14:10:00 PDT 2024
https://github.com/Sisyph updated https://github.com/llvm/llvm-project/pull/89288
>From 6ff20cec8f38c3f4ee8e3d6f02524170df8f982d Mon Sep 17 00:00:00 2001
From: Joe Nash <joseph.nash at amd.com>
Date: Wed, 17 Apr 2024 17:23:02 -0400
Subject: [PATCH] [AMDGPU] Create AMDGPUMnemonicAlias tablegen class
AMDGPUMnemonicAlias is a MnemonicAlias that inherits from
GCNPredicateControl, so that we can set predicates on the alias the same
way as Instructions.
Use AssemblerPredicate instead of Requires in aliases
NFC.
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 8 +++--
llvm/lib/Target/AMDGPU/BUFInstructions.td | 12 ++++++--
llvm/lib/Target/AMDGPU/DSInstructions.td | 34 ++++++++++++---------
llvm/lib/Target/AMDGPU/EXPInstructions.td | 6 +++-
llvm/lib/Target/AMDGPU/FLATInstructions.td | 14 ++++++---
llvm/lib/Target/AMDGPU/MIMGInstructions.td | 21 ++++++++-----
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 3 ++
llvm/lib/Target/AMDGPU/SMInstructions.td | 5 +--
llvm/lib/Target/AMDGPU/SOPInstructions.td | 28 ++++++++++++-----
llvm/lib/Target/AMDGPU/VOP1Instructions.td | 13 ++++----
llvm/lib/Target/AMDGPU/VOP2Instructions.td | 20 +++++++++---
llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 15 ++++++---
llvm/lib/Target/AMDGPU/VOPCInstructions.td | 26 +++++-----------
llvm/lib/Target/AMDGPU/VOPInstructions.td | 10 ++++--
14 files changed, 137 insertions(+), 78 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 9b09550159993c..d30508787c8d5f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1909,7 +1909,8 @@ def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
def HasTrue16BitInsts : Predicate<"Subtarget->hasTrue16BitInsts()">,
AssemblerPredicate<(all_of FeatureTrue16BitInsts)>;
-def NotHasTrue16BitInsts : True16PredicateClass<"!Subtarget->hasTrue16BitInsts()">;
+def NotHasTrue16BitInsts : True16PredicateClass<"!Subtarget->hasTrue16BitInsts()">,
+ AssemblerPredicate<(all_of (not FeatureTrue16BitInsts))>;
// Control use of True16 instructions. The real True16 instructions are
// True16 instructions as they are defined in the ISA. Fake True16
@@ -1918,7 +1919,10 @@ def NotHasTrue16BitInsts : True16PredicateClass<"!Subtarget->hasTrue16BitInsts()
def UseRealTrue16Insts : True16PredicateClass<"Subtarget->useRealTrue16Insts()">,
AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts)>;
def UseFakeTrue16Insts : True16PredicateClass<"Subtarget->hasTrue16BitInsts() && "
- "!Subtarget->useRealTrue16Insts()">;
+ "!Subtarget->useRealTrue16Insts()">,
+ AssemblerPredicate<(all_of FeatureTrue16BitInsts)>;
+ // FIXME When we default to RealTrue16 instead of Fake, change the line as follows.
+ // AssemblerPredicate<(all_of FeatureTrue16BitInsts, (not FeatureRealTrue16Insts))>;
def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
AssemblerPredicate<(all_of FeatureVOP3P)>;
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 8053d89aeb0a89..8eaa113ac18167 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -2456,13 +2456,19 @@ class get_BUF_ps<string name> {
// gfx11 instruction that accept both old and new assembler name.
class Mnem_gfx11_gfx12 <string mnemonic, string real_name> :
- MnemonicAlias<mnemonic, real_name>, Requires<[isGFX11Plus]>;
+ AMDGPUMnemonicAlias<mnemonic, real_name> {
+ let AssemblerPredicate = isGFX11Plus;
+}
class Mnem_gfx11 <string mnemonic, string real_name> :
- MnemonicAlias<mnemonic, real_name>, Requires<[isGFX11Only]>;
+ AMDGPUMnemonicAlias<mnemonic, real_name> {
+ let AssemblerPredicate = isGFX11Only;
+}
class Mnem_gfx12 <string mnemonic, string real_name> :
- MnemonicAlias<mnemonic, real_name>, Requires<[isGFX12Plus]>;
+ AMDGPUMnemonicAlias<mnemonic, real_name> {
+ let AssemblerPredicate = isGFX12Plus;
+}
multiclass MUBUF_Real_AllAddr_gfx11_Impl2<bits<8> op, string real_name> {
defm _BOTHEN : MUBUF_Real_gfx11<op, real_name>;
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 0773ef7f323418..de161f0e1ce9d1 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -1213,12 +1213,14 @@ class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
multiclass DS_Real_gfx12<bits<8> op, string name = !tolower(NAME), bit needAlias = true> {
defvar ps = !cast<DS_Pseudo>(NAME);
- let AssemblerPredicate = isGFX12Plus, DecoderNamespace = "GFX12" in
- def _gfx12 :
- Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
+ let AssemblerPredicate = isGFX12Plus in {
+ let DecoderNamespace = "GFX12" in
+ def _gfx12 :
+ Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
name, /*hasGDS=*/false>;
- if !and(needAlias, !ne(ps.Mnemonic, name)) then
- def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
+ if !and(needAlias, !ne(ps.Mnemonic, name)) then
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
+ } // End AssemblerPredicate
}
defm DS_MIN_F32 : DS_Real_gfx12<0x012, "ds_min_num_f32">;
@@ -1239,10 +1241,12 @@ defm DS_PK_ADD_BF16 : DS_Real_gfx12<0x09b>;
defm DS_PK_ADD_RTN_BF16 : DS_Real_gfx12<0x0ab>;
// New aliases added in GFX12 without renaming the instructions.
-def : MnemonicAlias<"ds_subrev_u32", "ds_rsub_u32">, Requires<[isGFX12Plus]>;
-def : MnemonicAlias<"ds_subrev_rtn_u32", "ds_rsub_rtn_u32">, Requires<[isGFX12Plus]>;
-def : MnemonicAlias<"ds_subrev_u64", "ds_rsub_u64">, Requires<[isGFX12Plus]>;
-def : MnemonicAlias<"ds_subrev_rtn_u64", "ds_rsub_rtn_u64">, Requires<[isGFX12Plus]>;
+let AssemblerPredicate = isGFX12Plus in {
+ def : AMDGPUMnemonicAlias<"ds_subrev_u32", "ds_rsub_u32">;
+ def : AMDGPUMnemonicAlias<"ds_subrev_rtn_u32", "ds_rsub_rtn_u32">;
+ def : AMDGPUMnemonicAlias<"ds_subrev_u64", "ds_rsub_u64">;
+ def : AMDGPUMnemonicAlias<"ds_subrev_rtn_u64", "ds_rsub_rtn_u64">;
+}
//===----------------------------------------------------------------------===//
// GFX11.
@@ -1250,12 +1254,14 @@ def : MnemonicAlias<"ds_subrev_rtn_u64", "ds_rsub_rtn_u64">, Requires<[isGFX12Pl
multiclass DS_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
defvar ps = !cast<DS_Pseudo>(NAME);
- let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in
- def _gfx11 :
- Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX11,
+ let AssemblerPredicate = isGFX11Only in {
+ let DecoderNamespace = "GFX11" in
+ def _gfx11 :
+ Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX11,
name>;
- if !ne(ps.Mnemonic, name) then
- def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
+ if !ne(ps.Mnemonic, name) then
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
+ } // End AssemblerPredicate
}
multiclass DS_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)>
diff --git a/llvm/lib/Target/AMDGPU/EXPInstructions.td b/llvm/lib/Target/AMDGPU/EXPInstructions.td
index b73b83031af0d6..e02652e62a5744 100644
--- a/llvm/lib/Target/AMDGPU/EXPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/EXPInstructions.td
@@ -117,12 +117,16 @@ multiclass EXP_Real_gfx11 {
multiclass VEXPORT_Real_gfx12 {
defvar ps = !cast<EXP_Pseudo>(NAME);
def _gfx12 : EXP_Real_Row<ps, SIEncodingFamily.GFX12, "export">,
- EXPe_Row, MnemonicAlias<"exp", "export">, Requires<[isGFX12Plus, HasExportInsts]> {
+ EXPe_Row {
let AssemblerPredicate = isGFX12Only;
let DecoderNamespace = "GFX12";
let row = ps.row;
let done = ps.done;
}
+ def : AMDGPUMnemonicAlias<"exp", "export"> {
+ let AssemblerPredicate = isGFX12Plus;
+ let OtherPredicates = [HasExportInsts];
+ }
}
defm EXP : EXP_Real_gfx11, VEXPORT_Real_gfx12;
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index 27d5616565f264..377d48a48e9b9f 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -2357,7 +2357,9 @@ multiclass FLAT_Real_gfx11 <bits<7> op,
multiclass FLAT_Aliases_gfx11<string name> {
defvar ps = get_FLAT_ps<NAME>;
if !ne(ps.Mnemonic, name) then
- def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
+ let AssemblerPredicate = isGFX11Only;
+ }
}
multiclass FLAT_Real_Base_gfx11<bits<7> op,
@@ -2544,10 +2546,12 @@ multiclass VFLAT_Real_gfx12 <bits<8> op, string name = get_FLAT_ps<NAME>.Mnemoni
multiclass VFLAT_Aliases_gfx12<string name, string alias = name> {
defvar ps = get_FLAT_ps<NAME>;
- if !ne(ps.Mnemonic, name) then
- def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Only]>;
- if !ne(alias, name) then
- def : MnemonicAlias<alias, name>, Requires<[isGFX12Only]>;
+ let AssemblerPredicate = isGFX12Only in {
+ if !ne(ps.Mnemonic, name) then
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
+ if !ne(alias, name) then
+ def : AMDGPUMnemonicAlias<alias, name>;
+ }
}
multiclass VFLAT_Real_Base_gfx12<bits<8> op,
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 23e8be0d5e45ea..9f6277f1257f78 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -963,11 +963,10 @@ class VIMAGE_Atomic_gfx12<mimgopc op, string opcode, RegisterClass DataRC,
let AsmString = opcode#" $vdata, "#AddrAsm#", $rsrc$dmask$dim$cpol$r128$a16$tfe";
}
-class VIMAGE_Atomic_gfx12_Renamed<mimgopc op, string opcode, string renamed,
+class VIMAGE_Atomic_gfx12_Renamed<mimgopc op, string renamed,
RegisterClass DataRC, int num_addrs,
bit enableDisasm = 0>
- : VIMAGE_Atomic_gfx12<op, renamed, DataRC, num_addrs, enableDisasm>,
- MnemonicAlias<opcode, renamed>, Requires<[isGFX12Plus, HasImageInsts]>;
+ : VIMAGE_Atomic_gfx12<op, renamed, DataRC, num_addrs, enableDisasm>;
multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
RegisterClass data_rc,
@@ -998,7 +997,7 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
if !empty(renamed) then
def _V1_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 1, enableDasm>;
else
- def _V1_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, asm, renamed, data_rc, 1, enableDasm>;
+ def _V1_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, renamed, data_rc, 1, enableDasm>;
}
}
let VAddrDwords = 2 in {
@@ -1023,7 +1022,7 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
if !empty(renamed) then
def _V2_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 2, 0>;
else
- def _V2_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, asm, renamed, data_rc, 2, 0>;
+ def _V2_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, renamed, data_rc, 2, 0>;
}
}
let VAddrDwords = 3 in {
@@ -1048,7 +1047,7 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
if !empty(renamed) then
def _V3_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 3, 0>;
else
- def _V3_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, asm, renamed, data_rc, 3, 0>;
+ def _V3_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, renamed, data_rc, 3, 0>;
}
}
let VAddrDwords = 4 in {
@@ -1073,10 +1072,18 @@ multiclass MIMG_Atomic_Addr_Helper_m <mimgopc op, string asm,
if !empty(renamed) then
def _V4_gfx12 : VIMAGE_Atomic_gfx12 <op, asm, data_rc, 4, enableDasm>;
else
- def _V4_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, asm, renamed, data_rc, 4, enableDasm>;
+ def _V4_gfx12 : VIMAGE_Atomic_gfx12_Renamed <op, renamed, data_rc, 4, enableDasm>;
}
}
}
+ if !and(op.HAS_GFX12, !not(!empty(renamed))) then
+ def : AMDGPUMnemonicAlias<asm, renamed> {
+ let AssemblerPredicate = isGFX12Plus;
+ let OtherPredicates = [HasImageInsts];
+ bit IsAtomicRet; // Unused
+ MIMGBaseOpcode BaseOpcode; // Unused
+ int VDataDwords; // Unused
+ }
}
multiclass MIMG_Atomic <mimgopc op, string asm, bit isCmpSwap = 0, bit isFP = 0,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index f1afbcc060b261..ecd7fd7a6f2f62 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -16,6 +16,9 @@ class GCNPredicateControl : PredicateControl {
Predicate VIAssemblerPredicate = isGFX8GFX9;
}
+class AMDGPUMnemonicAlias<string From, string To, string VariantName = "">
+ : MnemonicAlias<From, To, VariantName>, GCNPredicateControl;
+
// Except for the NONE field, this must be kept in sync with the
// SIEncodingFamily enum in SIInstrInfo.cpp and the columns of the
// getMCOpcodeGen table.
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index afc9da07bc96fa..40ba47f8877106 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -1332,8 +1332,9 @@ multiclass SM_Real_Loads_gfx11<bits<8> op, string ps> {
def _IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_IMM", opName>;
def _SGPR_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_SGPR", opName>;
def _SGPR_IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_SGPR_IMM", opName>;
- def : MnemonicAlias<!cast<SM_Pseudo>(ps#"_IMM").Mnemonic, opName>,
- Requires<[isGFX11Plus]>;
+ def : AMDGPUMnemonicAlias<!cast<SM_Pseudo>(ps#"_IMM").Mnemonic, opName> {
+ let AssemblerPredicate = isGFX11Plus;
+ }
}
defm S_LOAD_B32 : SM_Real_Loads_gfx11<0x000, "S_LOAD_DWORD">;
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 0b7d45ee8c027d..1bfe018306a9e6 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1974,7 +1974,9 @@ multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
def _gfx11 : SOP1_Real<op, ps, name>,
Select_gfx11<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
- def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
+ let AssemblerPredicate = isGFX11Only;
+ }
}
multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
@@ -1982,7 +1984,9 @@ multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
def _gfx12 : SOP1_Real<op, ps, name>,
Select_gfx12<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
- def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
+ let AssemblerPredicate = isGFX12Plus;
+ }
}
multiclass SOP1_M0_Real_gfx12<bits<8> op> {
@@ -2207,7 +2211,9 @@ multiclass SOP2_Real_gfx12<bits<7> op, string name = !tolower(NAME)> {
def _gfx12 : SOP2_Real32<op, ps, name>,
Select_gfx12<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
- def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
+ let AssemblerPredicate = isGFX12Plus;
+ }
}
defm S_MINIMUM_F32 : SOP2_Real_gfx12<0x04f>;
@@ -2224,7 +2230,9 @@ multiclass SOP2_Real_gfx11<bits<7> op, string name = !tolower(NAME)> {
def _gfx11 : SOP2_Real32<op, ps, name>,
Select_gfx11<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
- def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
+ let AssemblerPredicate = isGFX11Only;
+ }
}
multiclass SOP2_Real_gfx11_gfx12<bits<7> op, string name = !tolower(NAME)> :
@@ -2412,7 +2420,9 @@ multiclass SOPK_Real32_gfx12<bits<5> op, string name = !tolower(NAME)> {
def _gfx12 : SOPK_Real32<op, ps, name>,
Select_gfx12<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
- def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
+ let AssemblerPredicate = isGFX12Plus;
+ }
}
multiclass SOPK_Real32_gfx11<bits<5> op> {
@@ -2541,7 +2551,9 @@ multiclass SOPP_Real_32_gfx12<bits<7> op, string name = !tolower(NAME)> {
def _gfx12 : SOPP_Real_32<op, ps, name>,
Select_gfx12<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
- def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
+ let AssemblerPredicate = isGFX12Plus;
+ }
}
defm S_BARRIER_WAIT : SOPP_Real_32_gfx12<0x014>;
@@ -2567,7 +2579,9 @@ multiclass SOPP_Real_32_gfx11<bits<7> op, string name = !tolower(NAME)> {
Select_gfx11<ps.PseudoInstr>,
SOPPRelaxTable<0, ps.KeyName, "_gfx11">;
if !ne(ps.Mnemonic, name) then
- def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
+ let AssemblerPredicate = isGFX11Only;
+ }
}
multiclass SOPP_Real_64_gfx12<bits<7> op> {
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 2341e0d9d32bb4..cd1e94c73913bf 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -143,14 +143,14 @@ multiclass VOP1Inst <string opName, VOPProfile P,
def _e64_dpp : VOP3_DPP_Pseudo <opName, P>;
} // End SubtargetPredicate = isGFX11Plus
- def : MnemonicAlias<opName#"_e32", opName>, LetDummies;
- def : MnemonicAlias<opName#"_e64", opName>, LetDummies;
+ def : LetDummies, AMDGPUMnemonicAlias<opName#"_e32", opName>;
+ def : LetDummies, AMDGPUMnemonicAlias<opName#"_e64", opName>;
if P.HasExtSDWA then
- def : MnemonicAlias<opName#"_sdwa", opName>, LetDummies;
+ def : LetDummies, AMDGPUMnemonicAlias<opName#"_sdwa", opName>;
if P.HasExtDPP then
- def : MnemonicAlias<opName#"_dpp", opName, AMDGPUAsmVariants.DPP>, LetDummies;
+ def : LetDummies, AMDGPUMnemonicAlias<opName#"_dpp", opName, AMDGPUAsmVariants.DPP>;
}
multiclass VOP1Inst_t16<string opName,
@@ -858,8 +858,9 @@ multiclass VOP1_Real_NO_VOP3_with_name_gfx11<bits<9> op, string opName,
VOP1_Real_dpp_with_name<GFX11Gen, op, opName, asmName>,
VOP1_Real_dpp8_with_name<GFX11Gen, op, opName, asmName>;
defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");
- def gfx11_alias : MnemonicAlias<ps.Mnemonic, asmName>,
- Requires<[isGFX11Plus]>;
+ def gfx11_alias : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
+ let AssemblerPredicate = isGFX11Plus;
+ }
}
multiclass VOP1_Real_NO_VOP3_with_name_gfx12<bits<9> op, string opName,
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index c001c5de81e0b7..d2af1753d55039 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1510,7 +1510,9 @@ multiclass VOP2_Real_NO_VOP3_with_name<GFXGen Gen, bits<6> op, string opName,
VOP2_Real_dpp_with_name<Gen, op, opName, asmName>,
VOP2_Real_dpp8_with_name<Gen, op, opName, asmName>;
defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
- def Gen.Suffix#"_alias" : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>;
+ def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
+ let AssemblerPredicate = Gen.AssemblerPredicate;
+ }
}
multiclass VOP2_Real_FULL_with_name<GFXGen Gen, bits<6> op, string opName,
@@ -1523,13 +1525,17 @@ multiclass VOP2_Real_NO_DPP_with_name<GFXGen Gen, bits<6> op, string opName,
defm NAME : VOP2_Real_e32_with_name<Gen, op, opName, asmName>,
VOP2_Real_e64_with_name<Gen, op, opName, asmName>;
defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
- def Gen.Suffix#"_alias" : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>;
+ def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
+ let AssemblerPredicate = Gen.AssemblerPredicate;
+ }
}
multiclass VOP2_Real_NO_DPP_with_alias<GFXGen Gen, bits<6> op, string alias> {
defm NAME : VOP2_Real_e32<Gen, op>,
VOP2_Real_e64<Gen, op>;
- def Gen.Suffix#"_alias" : MnemonicAlias<alias, NAME>, Requires<[Gen.AssemblerPredicate]>;
+ def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<alias, NAME> {
+ let AssemblerPredicate = Gen.AssemblerPredicate;
+ }
}
//===----------------------------------------------------------------------===//
@@ -1550,7 +1556,9 @@ multiclass VOP2_Real_FULL_with_name_gfx12<bits<6> op, string opName,
multiclass VOP2_Real_FULL_t16_with_name_gfx12<bits<6> op, string opName,
string asmName, string alias> {
defm NAME : VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;
- def _gfx12_2nd_alias : MnemonicAlias<alias, asmName>, Requires<[isGFX12Only]>;
+ def _gfx12_2nd_alias : AMDGPUMnemonicAlias<alias, asmName> {
+ let AssemblerPredicate = isGFX12Only;
+ }
}
multiclass VOP2_Real_NO_DPP_with_name_gfx12<bits<6> op, string opName,
@@ -1609,7 +1617,9 @@ multiclass VOP2_Real_NO_VOP3_with_name_gfx11<bits<6> op, string opName,
VOP2_Real_dpp_with_name<GFX11Gen, op, opName, asmName>,
VOP2_Real_dpp8_with_name<GFX11Gen, op, opName, asmName>;
defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");
- def _gfx11_alias : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Only]>;
+ def _gfx11_alias : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
+ let AssemblerPredicate = isGFX11Only;
+ }
}
multiclass VOP2_Real_NO_DPP_with_name_gfx11<bits<6> op, string opName,
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index a7d63fdb2e04c8..fe992cf3776866 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -814,8 +814,8 @@ let isCommutable = 1, isReMaterializable = 1 in {
defm V_PK_MOV_B32 : VOP3PInst<"v_pk_mov_b32", VOP3P_Profile<VOP_V2I32_V2I32_V2I32, VOP3_PACKED>>;
} // End isCommutable = 1, isReMaterializable = 1
-def : MnemonicAlias<"v_accvgpr_read", "v_accvgpr_read_b32">;
-def : MnemonicAlias<"v_accvgpr_write", "v_accvgpr_write_b32">;
+def : AMDGPUMnemonicAlias<"v_accvgpr_read", "v_accvgpr_read_b32">;
+def : AMDGPUMnemonicAlias<"v_accvgpr_write", "v_accvgpr_write_b32">;
class VOPProfileWMMA<VOPProfile P, string Suffix, RegisterOperand _Src01RC64, bit _HasClamp, bit _HasOpSel> : VOP3P_Profile<P> {
let DstRC = !if(!eq(Suffix, "_w32"), VDst_256, VDst_128);
@@ -1481,8 +1481,11 @@ multiclass VOP3P_Real_with_name<GFXGen Gen, bits<7> op,
let AsmString = asmName # ps.AsmOperands in
def Gen.Suffix :
VOP3P_Real_Gen<!cast<VOP3P_Pseudo>(backing_ps_name), Gen, asmName>,
- VOP3Pe_gfx11_gfx12<op, !cast<VOP3P_Pseudo>(backing_ps_name).Pfl>,
- MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>;
+ VOP3Pe_gfx11_gfx12<op, !cast<VOP3P_Pseudo>(backing_ps_name).Pfl>;
+
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
+ let AssemblerPredicate = Gen.AssemblerPredicate;
+ }
}
multiclass VOP3P_Real_dpp<GFXGen Gen, bits<7> op, string backing_ps_name = NAME,
@@ -1661,7 +1664,9 @@ multiclass VOP3P_Real_SMFMAC<bits<7> op, string alias> {
let AssemblerPredicate = isGFX940Plus;
let DecoderNamespace = "GFX8";
}
- def : MnemonicAlias<alias, !cast<VOP3_Pseudo>(NAME#"_e64").Mnemonic>;
+ def : AMDGPUMnemonicAlias<alias, !cast<VOP3_Pseudo>(NAME#"_e64").Mnemonic> {
+ let AssemblerPredicate = isGFX940Plus;
+ }
}
let SubtargetPredicate = isGFX8GFX9 in {
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index a0d666b39b2bf9..ddd6d8b074aa3f 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -1389,17 +1389,12 @@ multiclass VOPC_Real_with_name<GFXGen Gen, bits<9> op, string OpName,
defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_e32");
defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_e64");
let AssemblerPredicate = Gen.AssemblerPredicate in {
- // MnemonicAlias and GCNPredicateControl both define the field Predicates,
- // so GCNPredicateControl must come after MnemonicAlias because it contains
- // the predicates we actually want.
- def : MnemonicAlias<!if(!empty(pseudo_mnemonic), ps32.Mnemonic,
+ def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), ps32.Mnemonic,
pseudo_mnemonic),
- asm_name, ps32.AsmVariantName>,
- GCNPredicateControl;
- def : MnemonicAlias<!if(!empty(pseudo_mnemonic), ps64.Mnemonic,
+ asm_name, ps32.AsmVariantName>;
+ def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), ps64.Mnemonic,
pseudo_mnemonic),
- asm_name, ps64.AsmVariantName>,
- GCNPredicateControl;
+ asm_name, ps64.AsmVariantName>;
let DecoderNamespace = Gen.DecoderNamespace in {
def _e32#Gen.Suffix :
@@ -1523,17 +1518,12 @@ multiclass VOPCX_Real_with_name<GFXGen Gen, bits<9> op, string OpName,
defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_nosdst_e32");
defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_nosdst_e64");
let AssemblerPredicate = Gen.AssemblerPredicate in {
- // MnemonicAlias and GCNPredicateControl both define the field Predicates,
- // so GCNPredicateControl must come after MnemonicAlias because it contains
- // the predicates we actually want.
- def : MnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps32.Mnemonic),
+ def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps32.Mnemonic),
pseudo_mnemonic),
- asm_name, ps32.AsmVariantName>,
- GCNPredicateControl;
- def : MnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps64.Mnemonic),
+ asm_name, ps32.AsmVariantName>;
+ def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps64.Mnemonic),
pseudo_mnemonic),
- asm_name, ps64.AsmVariantName>,
- GCNPredicateControl;
+ asm_name, ps64.AsmVariantName>;
let DecoderNamespace = Gen.DecoderNamespace in {
def _e32#Gen.Suffix
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index 60e91c7d858c8f..74f9bd899d51f5 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -1429,7 +1429,9 @@ multiclass VOP3_Real_with_name<GFXGen Gen, bits<10> op, string opName,
VOP3e_gfx11_gfx12<op, ps.Pfl>;
}
}
- def Gen.Suffix#"_VOP3_alias" : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[Gen.AssemblerPredicate]>, LetDummies;
+ def Gen.Suffix#"_VOP3_alias" : LetDummies, AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
+ let AssemblerPredicate = Gen.AssemblerPredicate;
+ }
}
// for READLANE/WRITELANE
@@ -1602,8 +1604,10 @@ multiclass VOP3be_Real_with_name_gfx12<bits<10> op, string opName,
IsSingle = !or(isSingle, ps.Pfl.IsSingle) in
def _e64_gfx12 :
VOP3_Real_Gen<ps, GFX12Gen, asmName>,
- VOP3be_gfx11_gfx12<op, ps.Pfl>,
- MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX12Only]>;
+ VOP3be_gfx11_gfx12<op, ps.Pfl>;
+ def : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {
+ let AssemblerPredicate = GFX12Gen.AssemblerPredicate;
+ }
}
multiclass VOP3_Realtriple_with_name_gfx12<bits<10> op, string opName,
More information about the llvm-commits
mailing list