[llvm] [RISCV][llvm-mca] Use Sched*MC for Zvk MC instructions and add Zvk tests for P600 (PR #89256)

[Craig Topper via llvm-commits]

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@@ -1,20 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
 
-vsetvli zero, zero, e32, mf8, tu, mu
-vsha2ms.vv v4, v8, v12
-vsha2ch.vv v4, v8, v12
-vsha2cl.vv v4, v8, v12
-
-vsetvli zero, zero, e32, mf4, tu, mu
-vsha2ms.vv v4, v8, v12
-vsha2ch.vv v4, v8, v12
-vsha2cl.vv v4, v8, v12
-
-vsetvli zero, zero, e32, mf2, tu, mu
-vsha2ms.vv v4, v8, v12
-vsha2ch.vv v4, v8, v12
-vsha2cl.vv v4, v8, v12
+# SEW is only e8 or e64
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topperc wrote:

e32 or e64?

https://github.com/llvm/llvm-project/pull/89256