[llvm] [DAG] Introduce generic shl_add node [NFC] (PR #88791)

[Philip Reames via llvm-commits]

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@@ -46905,12 +46897,18 @@ static SDValue reduceVMULWidth(SDNode *N, SelectionDAG &DAG,
   return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ResLo, ResHi);
 }
 
+static SDValue createMulImm(uint64_t MulAmt, SDValue N, SelectionDAG &DAG,
+                            EVT VT, const SDLoc &DL) {
+  assert(MulAmt == 3 || MulAmt == 5 || MulAmt == 9);
+  SDValue ShAmt = DAG.getConstant(Log2_64(MulAmt - 1), DL, MVT::i8);
+  return DAG.getNode(ISD::SHL_ADD, DL, VT, N, ShAmt, N);
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preames wrote:

Well, the news here is not good.  Adding in Freeze in the x86 backend code causes a whole bunch of regressions that were not obvious on first glance.  Interestingly, incorporating the same logic into the RISC-V specific version of this patch (https://github.com/llvm/llvm-project/pull/89263) doesn't seem to expose the same kind of problems - mostly likely because the usage is much more isolated.  https://github.com/llvm/llvm-project/pull/89290 fixes an analogous freeze issue in code already landed, again with no visible code diff.

I think what I'd like to suggest here is that we go ahead and focus review on https://github.com/llvm/llvm-project/pull/89263.  Once we land that, I can iterate in tree on the RISC-V specific parts, and then rebase this patch on a fully fleshed through implementation and focus it on the x86 merge.  (I clearly need to track something down there.)

(For the record, the issue @dtcxzyw flagged in the RISCV specific part of this patch doesn't exist in https://github.com/llvm/llvm-project/pull/89263 as I focused on a different subset there.  That's probably confusing for reviewers in retrospect, sorry!)

https://github.com/llvm/llvm-project/pull/88791