[llvm] [RISCV][llvm-mca] Use Sched*MC for Zvk MC instructions and add Zvk tests for P600 (PR #89256)

[Craig Topper via llvm-commits]

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@@ -57,29 +55,31 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
   def I : RVInstIVI_VROR<funct6, (outs VR:$vd),
               (ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
               opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
-         Sched<[WriteVIALUI_WorstCase, ReadVIALUV_WorstCase,
-                ReadVMask]>;
+          SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
 }
 
 // op vd, vs2, vs1
 class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : VALUVVNoVm<funct6, opv, opcodestr> {
+    : VALUVVNoVm<funct6, opv, opcodestr>,
+      SchedUnaryMC<"WriteVIALUI", "ReadVIALUV"> {
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topperc wrote:

This is inconsistent with how this is done in RISCVInstrInfoV.td. PALUVVNoVm is intended to be a special version of `VALUVVNoVm` with a different opcode. Since VALUVVNoVm doesn't contain a Sched*MC, `PALUVVNoVm` shouldn't either.

https://github.com/llvm/llvm-project/pull/89256